TLK10031

現行

單通道 XAUI/10GBASE-KR 收發器

TLK10031

現行

產品詳細資料

Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
FCBGA (CTR) 144 169 mm² (13 mm × 13 mm)
  • Single Channel Multi-Rate Transceiver
  • Supports 10GBASE-KR, XAUI, and 1GBASE-KX Ethernet Standards
  • Supports all CPRI and OBSAI Data Rates up to 10 Gbps
  • Supports Multi-Rate SERDES Operation with up to 10.3125 Gbps Data Rate on the High Speed Side and up to 5 Gbps on the Low Speed Side
  • Differential CML I/Os on Both High Speed and Low Speed Sides
  • Interface to Backplanes, Passive and Active Copper Cables, or SFP+ Optical Modules
  • Selectable Reference Clock with Multiple Output Clock Options
  • Supports PRBS, CRPAT, CJPAT, High/Low/Mixed-Frequency Patterns, and KR Pseudo-Random Pattern Generation and Verification, Square-Wave Generation
  • Supports Data Retime Operation
  • Two Power Supplies: 1 V (Core), and 1.5 or 1.8 V (I/O)
  • No Power Supply Sequencing Requirements
  • Transmit De-emphasis and Receive Adaptive Equalization to Allow Extended Backplane/Cable Reach on Both High Speed and Low Speed Sides
  • Loss of Signal (LOS) Detection
  • Supports 10G-KR Link Training, Forward Error Correction, Auto-Negotiation
  • Jumbo Packet Support
  • JTAG; IEEE 1149.1 Test Interface
  • Industry Standard MDIO Control Interface
  • 65nm Advanced CMOS Technology
  • Industrial Ambient Operating Temperature (–40°C to 85°C)
  • Power Consumption: 800 mW (Nominal)
  • Single Channel Multi-Rate Transceiver
  • Supports 10GBASE-KR, XAUI, and 1GBASE-KX Ethernet Standards
  • Supports all CPRI and OBSAI Data Rates up to 10 Gbps
  • Supports Multi-Rate SERDES Operation with up to 10.3125 Gbps Data Rate on the High Speed Side and up to 5 Gbps on the Low Speed Side
  • Differential CML I/Os on Both High Speed and Low Speed Sides
  • Interface to Backplanes, Passive and Active Copper Cables, or SFP+ Optical Modules
  • Selectable Reference Clock with Multiple Output Clock Options
  • Supports PRBS, CRPAT, CJPAT, High/Low/Mixed-Frequency Patterns, and KR Pseudo-Random Pattern Generation and Verification, Square-Wave Generation
  • Supports Data Retime Operation
  • Two Power Supplies: 1 V (Core), and 1.5 or 1.8 V (I/O)
  • No Power Supply Sequencing Requirements
  • Transmit De-emphasis and Receive Adaptive Equalization to Allow Extended Backplane/Cable Reach on Both High Speed and Low Speed Sides
  • Loss of Signal (LOS) Detection
  • Supports 10G-KR Link Training, Forward Error Correction, Auto-Negotiation
  • Jumbo Packet Support
  • JTAG; IEEE 1149.1 Test Interface
  • Industry Standard MDIO Control Interface
  • 65nm Advanced CMOS Technology
  • Industrial Ambient Operating Temperature (–40°C to 85°C)
  • Power Consumption: 800 mW (Nominal)

The TLK10031 is a single-channel multi-rate transceiver intended for use in high-speed bi-directional point-to-point data transmission systems. This device supports three primary modes. It can be used as a XAUI to 10GBASE-KR transceiver, as a general-purpose 8b/10b multi-rate 4:1, 2:1, or 1:1 serializer/deserializer, or can be used in 1G-KX mode.

The TLK10031 is a single-channel multi-rate transceiver intended for use in high-speed bi-directional point-to-point data transmission systems. This device supports three primary modes. It can be used as a XAUI to 10GBASE-KR transceiver, as a general-purpose 8b/10b multi-rate 4:1, 2:1, or 1:1 serializer/deserializer, or can be used in 1G-KX mode.

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver datasheet (Rev. C) PDF | HTML 2017/9/6

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開發板

TLK10232EVM — TLK10232EVM - 適用於 TLK10232 的主機板評估模組

Motherboard evaluation board for TLK10232 comes with custom-developed GUI and a detailed EVM user guide. This EVM along with the GUI, enable customers to configure the registers of all the channels independently and to debug the device. The user’s guide provides guidance on proper use of the (...)
使用指南: PDF
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FCBGA (CTR) 144 Ultra Librarian

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