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TPS51200A-Q1

現行

汲極和源極 DDR 終端穩壓器

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產品規格表

TPS51200A-Q1

現行
產品規格表 立即訂購

產品詳細資料

Vin (min) (V) 1.1 Vin (max) (V) 3.5 Vout (min) (V) -0.3 Vout (max) (V) 3.6 Features S3/S5 Support Iq (typ) (mA) 0.5 Rating Automotive Operating temperature range (°C) -40 to 125 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3
Vin (min) (V) 1.1 Vin (max) (V) 3.5 Vout (min) (V) -0.3 Vout (max) (V) 3.6 Features S3/S5 Support Iq (typ) (mA) 0.5 Rating Automotive Operating temperature range (°C) -40 to 125 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3
VSON (DRC) 10 9 mm² 3 x 3
  • AEC-Q100 Qualified for Automotive Applications:
    • Device Temperature Grade 1:
      –40°C ≤ TA ≤ 125°C
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C4B
  • Extended Reliability Testing
  • Input Voltage: Supports 2.5-V Rail and 3.3-V Rail
  • VLDOIN Voltage Range: 1.1 V to 3.5 V
  • Sink and Source Termination Regulator Includes Droop Compensation
  • Requires Minimum Output Capacitance of 20-µF (typically 3 × 10-µF MLCCs) for Memory Termination Applications (DDR)
  • PGOOD to Monitor Output Regulation
  • EN Input
  • REFIN Input Allows for Flexible Input Tracking Either Directly or Through Resistor Divider
  • Remote Sensing (VOSNS)
  • ±10-mA Buffered Reference (REFOUT)
  • Built-in Soft-Start, UVLO and OCL
  • Thermal Shutdown
  • Meets DDR, DDR2 JEDEC Specifications; Supports DDR3 and Low-Power DDR3 and DDR4 VTT Applications
  • VSON-10 Package With Exposed Thermal Pad
  • AEC-Q100 Qualified for Automotive Applications:
    • Device Temperature Grade 1:
      –40°C ≤ TA ≤ 125°C
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C4B
  • Extended Reliability Testing
  • Input Voltage: Supports 2.5-V Rail and 3.3-V Rail
  • VLDOIN Voltage Range: 1.1 V to 3.5 V
  • Sink and Source Termination Regulator Includes Droop Compensation
  • Requires Minimum Output Capacitance of 20-µF (typically 3 × 10-µF MLCCs) for Memory Termination Applications (DDR)
  • PGOOD to Monitor Output Regulation
  • EN Input
  • REFIN Input Allows for Flexible Input Tracking Either Directly or Through Resistor Divider
  • Remote Sensing (VOSNS)
  • ±10-mA Buffered Reference (REFOUT)
  • Built-in Soft-Start, UVLO and OCL
  • Thermal Shutdown
  • Meets DDR, DDR2 JEDEC Specifications; Supports DDR3 and Low-Power DDR3 and DDR4 VTT Applications
  • VSON-10 Package With Exposed Thermal Pad

The TPS51200A-Q1 device is a sink and source double-data-rate (DDR) termination regulator specifically designed for low input voltage, low-cost, low-noise systems where space is a key consideration.

The device maintains a fast transient response and only requires a minimum output capacitance of 20 µF. The device supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, and Low Power DDR3 and DDR4 VTT bus termination.

In addition, the device provides an open-drain PGOOD signal to monitor the output regulation and an EN signal that can be used to discharge VTT during S3 (suspend to RAM) for DDR applications.

The device is available in the thermally-efficient VSON-10 package, and is rated both green and Pb-free. The device is specified from –40°C to 125°C.

The TPS51200A-Q1 device is a sink and source double-data-rate (DDR) termination regulator specifically designed for low input voltage, low-cost, low-noise systems where space is a key consideration.

The device maintains a fast transient response and only requires a minimum output capacitance of 20 µF. The device supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, and Low Power DDR3 and DDR4 VTT bus termination.

In addition, the device provides an open-drain PGOOD signal to monitor the output regulation and an EN signal that can be used to discharge VTT during S3 (suspend to RAM) for DDR applications.

The device is available in the thermally-efficient VSON-10 package, and is rated both green and Pb-free. The device is specified from –40°C to 125°C.
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類型 標題 日期
* Data sheet TPS51200A-Q1 Sink and Source DDR Termination Regulator datasheet (Rev. A) PDF | HTML 2018年 12月 13日
Application note DDR VTT Power Solutions: A Competitive Analysis (Rev. A) 2020年 7月 9日

設計與開發

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開發板

TPS51200EVM — TPS51200 汲極源極 DDR 終端穩壓器

TPS51200EVM 評估板 HPA322A 旨在評估 TI 成本最佳化的 DDR/DDR2/DDR3/LP DDR3 VTT 終端穩壓器 TPS51200 的性能和特性。TPS51200 旨在為 DDR 記憶體提供適當的終止電壓與 10-mA 緩衝參考電壓，該電壓涵蓋 DDR (2.5 V/1.25 V)、DDR2 (1.8 V/0.9 V)、DDR3 (1.5 V/0.75 V)、LP DDR3 (1.2 V/0.6 V) 規格，且僅需最少外部零組件。

使用指南: PDF
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電路圖: PDF
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