The TPS51200EVM evaluation board, HPA322A is designed to evaluate the performance andcharacteristics of TI's cost optimized DDR/DDR2/DDR3/LP DDR3 VTT termination regulator, the TPS51200. The TPS51200 is designed to provide proper termination voltage and a 10-mA buffered reference voltage for DDR memory which covered DDR (2.5 V/1.25 V), DDR2 (1.8 V/0.9 V), DDR3 (1.5 V/0.75 V), LP DDR3 (1.2 V/0.6 V) specifications with minimal external components.
- Input Voltage: Support 2.5V Rail and 3.3V Rail
- VLDOIN, VDDQ Voltage Range: 1.2V-2.5V
- Build-in transient load switches (with both sinking and sourcing capability) to emulate the sink/source transient behavior which helps to evaluate the dynamic performance. For ease of use, both load step and timing of transient can be modified by on board resistors, and current information can also be monitored on board.
- DDR: +/-1.67 A Sink/Source Transient Load
- DDR2: +/-1.2 A Sink/Source Transient Load
- DDR3: +/-1.0 A Sink/Source Transient Load
- LP DDR3: +/-0.8 A Sink/Source Transient Load
- Switcher S1 for enable function
- Convenient test points for probing PGOOD, CLK_IN and loop response testing
- 2-layer PCB with all the components on the bottom side