ADC34J24EVM

ADC34J24 Quad-Channel, 12-Bit, 125-MSPS Analog-to-Digital Converter Evaluation Module

ADC34J24EVM

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Overview

The ADC34J24EVM Evaluation Module demonstrates the performance of a low power quad 125Msps 12 bit ADC. It includes the ADC34J24 device, JESD204B clocking is provided by the LMK04828 and TI voltage regulators to provide the necessary voltages. The input for the ADC is by default connected to the transformer input which can be connected to a 50 ohm single ended signal source. The clock reference input is provided via a transformer input and can be connected to a 50 ohm single ended clock source. An onboard LMK04828 can be used to generate the necessary JESD204B clocks. Register access is provided through the on board USB connection and a GUI.

Features
  • Single 1.8V supply to simplify power requirements
  • Flexible input clock buffer with 1/2/4 divider to simplify clocking
  • On chip dither to improve SFDR
  • JESD204B data interface to simplify digital interface, compliant up to 3.2Gbps lane rates
  • Supports subclasses 0, 1, 2 for synchronization and compatibility
  • Pin compatibility with 12/14b and dual/quad devices
High-speed ADCs (>10MSPS)
ADC34J24 Quad-Channel, 12-Bit, 125-MSPS Analog-to-Digital Converter (ADC)

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Evaluation board

ADC34J24EVM – ADC34J24 Evaluation Module

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Design files

ADC3xJxxEVM Design Package (Rev. A) SLAR094A.ZIP (11316 KB)

Technical documentation

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Type Title Date
Certificate ADC34J24EVM EU Declaration of Conformity (DoC) Jan. 02, 2019
User guide ADC3xxxEVM and ADC3xJxxEVM User's Guide (Rev. D) Aug. 24, 2018

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