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Product details

Parameters

Sample rate (Max) (MSPS) 160 Resolution (Bits) 14 Number of input channels 2 Interface JESD204B Analog input BW (MHz) 450 Features Low Power Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 454 Architecture Pipeline SNR (dB) 72.8 ENOB (Bits) 11.8 SFDR (dB) 96 Operating temperature range (C) -40 to 85 Input buffer No open-in-new Find other High-speed ADCs (>10MSPS)

Package | Pins | Size

VQFN (RGZ) 48 49 mm² 7 x 7 open-in-new Find other High-speed ADCs (>10MSPS)

Features

  • Dual Channel
  • 14-Bit Resolution
  • Single Supply: 1.8 V
  • Flexible Input Clock Buffer with Divide-by-1, -2, -4
  • SNR = 72.2 dBFS, SFDR = 87 dBc at
    fIN = 70 MHz
  • Ultralow Power Consumption:
    • 227 mW/Ch at 160 MSPS
  • Channel Isolation: 105 dB
  • Internal Dither
  • JESD204B Serial Interface:
    • Subclass 0, 1, 2 Compliant up to 3.2 Gbps
    • Supports One Lane per ADC up to 160 MSPS
  • Support for Multichip Synchronization
  • Pin-to-Pin Compatible with 12-Bit Version
    (ADC32J2X)
  • Package: VQFN-48 (7 mm × 7 mm)
open-in-new Find other High-speed ADCs (>10MSPS)

Description

The ADC32J4x are a high-linearity, ultra-low power, dual-channel, 14-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC32J4x family supports JESD204B interface in order to reduce the number of interface lines, thus allowing high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock, which is used to serialize the 14-bit data from each channel. The devices support subclass 1 with interface speeds up to 3.2 Gbps.

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Technical documentation

= Featured
No results found. Please clear your search and try again. View all 3
Type Title Date
* Datasheet ADC32J4x Dual-Channel, 14-Bit, 50-MSPS to 160-MSPS, Analog-to-Digital Converters with JESD204B Interface datasheet (Rev. A) May 26, 2015
User guides ADC3xxxEVM and ADC3xJxxEVM User's Guide (Rev. D) Aug. 24, 2018
User guides Optical Front-End System Design Guide Oct. 26, 2015

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
Description

The ADC32J45 EVM demonstrates the performance of a low power dual 160Msps 14 bit ADC. It includes the ADC32J45 device, LMK04828 JESD204B clocking solution and TI voltage regulators to provide the necessary voltages. The input for the ADC is connected to a transformer input which can be connected to (...)

Features
  • Single 1.8V supply to simplify power requirements
  • Flexible input clock buffer with 1/2/4 divider to simplify clocking
  • On chip dither to improve SFDR
  • JESD204B data interface to simplify digital interface, compliant up to 3.2Gbps lane rates
  • Supports subclasses 0,1,2 for synchronization and compatibility
  • (...)
EVALUATION BOARDS Download
document-generic User guide
Description

The ADC34J45 EVM demonstrates the performance of a low power quad 160Msps 14 bit ADC. It includes the ADC34J45 device, LMK04828 JESD204B clocking solution and TI voltage regulators to provide the necessary voltages. The input for the ADC is connected to a transformer input which can be connected to (...)

Features
  • Single 1.8V supply to simplify power requirements
  • Flexible input clock buffer with 1/2/4 divider to simplify clocking
  • On chip dither to improve SFDR
  • JESD204B data interface to simplify digital interface, compliant up to 3.2Gbps lane rates
  • Supports subclasses 0,1,2 for synchronization and compatibility
  • (...)

Design tools & simulation

SIMULATION MODELS Download
SBAM204.ZIP (79 KB) - IBIS Model
GERBER FILES Download
SBAC206.ZIP (8685 KB)

Reference designs

REFERENCE DESIGNS Download
High Perf Single Ended to Diff Active Interface for High Speed ADC Developed by Dallas Logic Corp
Provided by Dallas Logic Corporation This reference design uses the ADC34J22 12b 50Msps JESD204B data converter and the THS4541 fully differential amplifer to demonstrate how to design a high performance active interface for high speed ADCs.  This type of circuit can be used in sensor front end, motor control, and test and (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
VQFN (RGZ) 48 View options

Ordering & quality

Support & training

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