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High-speed ADCs (≥10 MSPS)

ADC34J45

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Quad-Channel, 14-Bit, 160-MSPS Analog-to-Digital Converter (ADC)

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Data sheet

ADC34J45

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 160 Resolution (Bps) 14 Number of input channels 4 Interface type JESD204B Analog input BW (MHz) 450 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 812 Architecture Pipeline SNR (dB) 72.7 ENOB (Bps) 11.8 SFDR (dB) 88 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 160 Resolution (Bps) 14 Number of input channels 4 Interface type JESD204B Analog input BW (MHz) 450 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 812 Architecture Pipeline SNR (dB) 72.7 ENOB (Bps) 11.8 SFDR (dB) 88 Operating temperature range (°C) -40 to 85 Input buffer No
VQFN (RGZ) 48 49 mm² 7 x 7
  • Quad Channel
  • 14-Bit Resolution
  • Single 1.8-V Supply
  • Flexible Input Clock Buffer with Divide-by-1, -2, -4
  • SNR = 72 dBFS, SFDR = 86 dBc at
    fIN = 70 MHz
  • Ultra-Low Power Consumption:
    • 203 mW/Ch at 160 MSPS
  • Channel Isolation: 105 dB
  • Internal Dither
  • JESD204B Serial Interface:
    • Supports Subclass 0, 1, 2
    • Supports One Lane per ADC up to 160 MSPS
  • Support for Multi-Chip Synchronization
  • Pin-to-Pin Compatible with 12-Bit Version
  • Package: VQFN-48 (7 mm × 7 mm)
  • Quad Channel
  • 14-Bit Resolution
  • Single 1.8-V Supply
  • Flexible Input Clock Buffer with Divide-by-1, -2, -4
  • SNR = 72 dBFS, SFDR = 86 dBc at
    fIN = 70 MHz
  • Ultra-Low Power Consumption:
    • 203 mW/Ch at 160 MSPS
  • Channel Isolation: 105 dB
  • Internal Dither
  • JESD204B Serial Interface:
    • Supports Subclass 0, 1, 2
    • Supports One Lane per ADC up to 160 MSPS
  • Support for Multi-Chip Synchronization
  • Pin-to-Pin Compatible with 12-Bit Version
  • Package: VQFN-48 (7 mm × 7 mm)

The ADC34J4x is a high-linearity, ultra-low power, quad-channel, 14-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC). The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization. The ADC34J4x family supports serial current-mode logic (CML) and JESD204B interfaces in order to reduce the number of interface lines, thus allowing high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock that is used to serialize the 14-bit data from each channel. The ADC34J4x devices support subclass 1 with interface speeds up to 3.2 Gbps.

The ADC34J4x is a high-linearity, ultra-low power, quad-channel, 14-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC). The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization. The ADC34J4x family supports serial current-mode logic (CML) and JESD204B interfaces in order to reduce the number of interface lines, thus allowing high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock that is used to serialize the 14-bit data from each channel. The ADC34J4x devices support subclass 1 with interface speeds up to 3.2 Gbps.
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Technical documentation

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Type Title Date
* Data sheet ADC34J4x Quad-Channel, 14-Bit, 50-MSPS to 160-MSPS, Analog-to-Digital Converter with a JESD204B Interface datasheet (Rev. B) PDF | HTML 10 Nov 2014
Application note Time of Flight and LIDAR - Optical Front End Design (Rev. A) PDF | HTML 29 Apr 2022
EVM User's guide ADC3xxxEVM and ADC3xJxxEVM User's Guide (Rev. D) 24 Aug 2018
White paper Minimum Power Specifications for High-Performance ADC Power-Supply Designs 31 Mar 2016
Design guide Optical Front-End System Design Guide 26 Oct 2015

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADC34J45EVM — ADC34J45 Quad-Channel, 14-Bit, 160-MSPS Analog-to-Digital Converter Evaluation Module

The ADC34J45 EVM demonstrates the performance of a low power quad 160Msps 14 bit ADC. It includes the ADC34J45 device, LMK04828 JESD204B clocking solution and TI voltage regulators to provide the necessary voltages. The input for the ADC is connected to a transformer input which can be connected to (...)

User guide: PDF
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Firmware

TI-JESD204-IP — JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
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Simulation model

ADC34J45 IBIS Model

SBAM204.ZIP (79 KB) - IBIS Model
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Simulation model

ADC34J45 IBIS-AMI Model

SBAM324.ZIP (1180 KB) - IBIS-AMI Model
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Simulation model

ADC3xJxx Pspice Model

SLAM231.ZIP (14 KB) - PSpice Model
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Simulation model

ADC3xJxx TINA Model

SLAM229.ZIP (4 KB) - TINA-TI Spice Model
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Simulation model

ADC3xJxx TINA Reference Design

SLAM230.TSC (1083 KB) - TINA-TI Reference Design
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Reference designs

TIDA-00725 — Wide Bandwidth Optical Front-end Reference Design

This reference design implements and measures a complete 120MHz wide bandwidth optical front end comprising a high speed transimpedance amplifier, fully differential amplifier, and high speed 14-bit 160MSPS ADC with JESD204B interface.  Hardware and software are provided to evaluate the (...)
Design guide: PDF
Schematic: PDF
Package Pins Download
VQFN (RGZ) 48 View options

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