The ADC34J4x is a high-linearity, ultra-low power, quad-channel, 14-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC). The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization. The ADC34J4x family supports serial current-mode logic (CML) and JESD204B interfaces in order to reduce the number of interface lines, thus allowing high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock that is used to serialize the 14-bit data from each channel. The ADC34J4x devices support subclass 1 with interface speeds up to 3.2 Gbps.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | ADC34J4x Quad-Channel, 14-Bit, 50-MSPS to 160-MSPS, Analog-to-Digital Converter with a JESD204B Interface datasheet (Rev. B) | PDF | HTML | Nov 10, 2014 |
| Application brief | Time of Flight and LIDAR - Optical Front End Design (Rev. A) | PDF | HTML | Apr 29, 2022 | |
| White paper | Minimum Power Specifications for High-Performance ADC Power-Supply Designs | Mar 31, 2016 | ||
| Design guide | Optical Front-End System Design Guide | Oct 26, 2015 |
For additional terms or required resources, click any title below to view the detail page where available.
The ADC34J45 EVM demonstrates the performance of a low power quad 160Msps 14 bit ADC. It includes the ADC34J45 device, LMK04828 JESD204B clocking solution and TI voltage regulators to provide the necessary voltages. The input for the ADC is connected to a transformer input which can be connected to (...)
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
This reference design implements and measures a complete 120MHz wide bandwidth optical front end comprising a high speed transimpedance amplifier, fully differential amplifier, and high speed 14-bit 160MSPS ADC with JESD204B interface. Hardware and software are provided to evaluate the (...)
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| VQFN (RGZ) | 48 | Ultra Librarian |
Recommended products may have parameters, evaluation modules or reference designs related to this TI product.
Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.
If you have questions about quality, packaging or ordering TI products, see TI support.