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Product details

Parameters

Sample rate (Max) (MSPS) 160 Resolution (Bits) 14 Number of input channels 4 Interface type JESD204B Analog input BW (MHz) 450 Features Low Power Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 812 Architecture Pipeline SNR (dB) 72.7 ENOB (Bits) 11.8 SFDR (dB) 88 Operating temperature range (C) -40 to 85 Input buffer No open-in-new Find other High-speed ADCs (>10MSPS)

Package | Pins | Size

VQFN (RGZ) 48 49 mm² 7 x 7 open-in-new Find other High-speed ADCs (>10MSPS)

Features

  • Quad Channel
  • 14-Bit Resolution
  • Single 1.8-V Supply
  • Flexible Input Clock Buffer with Divide-by-1, -2, -4
  • SNR = 72 dBFS, SFDR = 86 dBc at
    fIN = 70 MHz
  • Ultra-Low Power Consumption:
    • 203 mW/Ch at 160 MSPS
  • Channel Isolation: 105 dB
  • Internal Dither
  • JESD204B Serial Interface:
    • Supports Subclass 0, 1, 2
    • Supports One Lane per ADC up to 160 MSPS
  • Support for Multi-Chip Synchronization
  • Pin-to-Pin Compatible with 12-Bit Version
  • Package: VQFN-48 (7 mm × 7 mm)
open-in-new Find other High-speed ADCs (>10MSPS)

Description

The ADC34J4x is a high-linearity, ultra-low power, quad-channel, 14-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC). The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization. The ADC34J4x family supports serial current-mode logic (CML) and JESD204B interfaces in order to reduce the number of interface lines, thus allowing high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock that is used to serialize the 14-bit data from each channel. The ADC34J4x devices support subclass 1 with interface speeds up to 3.2 Gbps.

open-in-new Find other High-speed ADCs (>10MSPS)
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Technical documentation

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Type Title Date
* Datasheet ADC34J4x Quad-Channel, 14-Bit, 50-MSPS to 160-MSPS, Analog-to-Digital Converter with a JESD204B Interface datasheet (Rev. B) Nov. 10, 2014
Technical articles Keys to quick success using high-speed data converters Oct. 13, 2020
Application notes Time of Flight and LIDAR - Optical Front End Design Feb. 04, 2020
Technical articles How to achieve fast frequency hopping Mar. 03, 2019
User guides ADC3xxxEVM and ADC3xJxxEVM User's Guide (Rev. D) Aug. 24, 2018
Technical articles RF sampling: Learning more about latency Feb. 09, 2017
Technical articles Why phase noise matters in RF sampling converters Nov. 28, 2016
White papers Minimum Power Specifications for High-Performance ADC Power-Supply Designs Mar. 31, 2016
User guides Optical Front-End System Design Guide Oct. 26, 2015

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
Description

The ADC34J45 EVM demonstrates the performance of a low power quad 160Msps 14 bit ADC. It includes the ADC34J45 device, LMK04828 JESD204B clocking solution and TI voltage regulators to provide the necessary voltages. The input for the ADC is connected to a transformer input which can be connected to (...)

Features
  • Single 1.8V supply to simplify power requirements
  • Flexible input clock buffer with 1/2/4 divider to simplify clocking
  • On chip dither to improve SFDR
  • JESD204B data interface to simplify digital interface, compliant up to 3.2Gbps lane rates
  • Supports subclasses 0,1,2 for synchronization and compatibility
  • (...)

Software development

FIRMWARE Download
JESD204 rapid design IP for FPGAs connected to TI high-speed data converters
TI-JESD204-IP The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
Features
  • Compatible with JEDEC JESD204a/b/c protocols
  • Supports subclass 1 deterministic latency and multidevice synchronization
  • Supported lane rates
    • Up to 16.375 Gbps in 8b/10b mode
    • Up to 20 Gbps in 64b/66b mode
  • Supports all protocol related error detection and reporting features
  • Integrated transport layer (...)

Design tools & simulation

SIMULATION MODELS Download
SBAM204.ZIP (79 KB) - IBIS Model
SIMULATION MODELS Download
SBAM324.ZIP (1180 KB) - IBIS-AMI Model
SIMULATION MODELS Download
SLAM229.ZIP (4 KB) - TINA-TI Spice Model
SIMULATION MODELS Download
SLAM230.TSC (1083 KB) - TINA-TI Reference Design
SIMULATION MODELS Download
SLAM231.ZIP (14 KB) - PSpice Model
SIMULATION TOOLS Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
GERBER FILES Download
SBAC206.ZIP (8685 KB)

Reference designs

REFERENCE DESIGNS Download
Wide Bandwidth Optical Front-end Reference Design
TIDA-00725 This reference design implements and measures a complete 120MHz wide bandwidth optical front end comprising a high speed transimpedance amplifier, fully differential amplifier, and high speed 14-bit 160MSPS ADC with JESD204B interface.  Hardware and software are provided to evaluate the (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
VQFN (RGZ) 48 View options

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