Product details

Sample rate (Max) (MSPS) 125 Resolution (Bits) 14 Number of input channels 2 Interface type Serial LVDS Analog input BW (MHz) 540 Features Low Power Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 232 Architecture Pipeline SNR (dB) 73.3 ENOB (Bits) 11.8 SFDR (dB) 94 Operating temperature range (C) -40 to 85 Input buffer No
Sample rate (Max) (MSPS) 125 Resolution (Bits) 14 Number of input channels 2 Interface type Serial LVDS Analog input BW (MHz) 540 Features Low Power Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 232 Architecture Pipeline SNR (dB) 73.3 ENOB (Bits) 11.8 SFDR (dB) 94 Operating temperature range (C) -40 to 85 Input buffer No
VQFN (RGZ) 48 49 mm² 7 x 7
  • Dual Channel
  • 14-Bit Resolution
  • Single Supply: 1.8 V
  • Serial LVDS Interface (SLVDS)
  • Flexible Input Clock Buffer with Divide-by-1, -2, -4
  • SNR = 72.4 dBFS, SFDR = 87 dBc at
    fIN = 70 MHz
  • Ultra-Low Power Consumption:
    • 116 mW/Ch at 125 MSPS
  • Channel Isolation: 105 dB
  • Internal Dither and Chopper
  • Support for Multi-Chip Synchronization
  • Pin-to-Pin Compatible with 12-Bit Version
  • Package: VQFN-48 (7 mm × 7 mm)
  • Dual Channel
  • 14-Bit Resolution
  • Single Supply: 1.8 V
  • Serial LVDS Interface (SLVDS)
  • Flexible Input Clock Buffer with Divide-by-1, -2, -4
  • SNR = 72.4 dBFS, SFDR = 87 dBc at
    fIN = 70 MHz
  • Ultra-Low Power Consumption:
    • 116 mW/Ch at 125 MSPS
  • Channel Isolation: 105 dB
  • Internal Dither and Chopper
  • Support for Multi-Chip Synchronization
  • Pin-to-Pin Compatible with 12-Bit Version
  • Package: VQFN-48 (7 mm × 7 mm)

The ADC324x are a high-linearity, ultra-low power, dual-channel, 14-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC324x family supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.

The ADC324x are a high-linearity, ultra-low power, dual-channel, 14-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC324x family supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.

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Technical documentation

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Type Title Date
* Data sheet ADC324x Dual-Channel, 14-Bit, 25-MSPS to 125-MSPS, Analog-to-Digital Converters datasheet (Rev. C) PDF | HTML 22 Mar 2016
EVM User's guide ADC3xxxEVM and ADC3xJxxEVM User's Guide (Rev. D) 24 Aug 2018
Technical article It’s time for an upgrade: CMOS ADC with chopper 09 Nov 2015

Design & development

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Evaluation board

ADC3244EVM — ADC3244 dual-channel 14-bit 125-MSPS ADC evaluation module

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The input for the ADC is (...)

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Simulation model

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VQFN (RGZ) 48 View options

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