This reference design implements a hardware interface based on the BiSS standard for position or rotary encoders. It supports both BiSS point-to-point and BiSS bus configurations. The building blocks include the power supply for a 5-V BiSS encoder with innovative smart eFuse technology and robust full-duplex RS-485 transceivers including line termination and EMC protection. An auxiliary power supply and logic level interface with adjustable I/O voltage level is provided to connect to subsequent MCUs and MPUs that would run the BiSS (or SSI) master protocol stack. This design is fully tested to meet EMC immunity requirements for ESD, fast-transient burst and surge according to IEC61800-3.
- 3.3-V RS-485 full-duplex transceivers with IEC-ESD meets BiSS clock frequency (10 Mhz)
- Design meets EMC immunity requirements for ESD, fast transient burst and surge according to IEC61800-3
- Wide input (15 to 30 VDC) high-efficiency (>85%) DC/DC power supply for 5-V BiSS (or SSI) encoders with 35 0mA, lowest-ripple (<20-mVpp) output
- Protected power supply with innovative eFuse technology with inrush current limitation and protection against over-current, over- and under-voltage and disconnect in case of fault
- Option to shut down encoder power supply in case of fault or to save power when no encoder is connected
- 3.3-V interface with level shifter to also support 2.5-V or 1.8-V I/O interface to processors to run the BiSS (or SSI) master