TIDEP0022
ARM MPU with Integrated BiSS C Master Interface Reference Design
TIDEP0022
Overview
Implementation of BiSS C Master protocol on Industrial Communication Sub-System (PRU-ICSS). The design provides full documentation and source code for Programmable Realtime Unit (PRU).
Features
- BiSS C Master protocol running on ICSS
- Interface speed of 1, 2, 5 and 10 MHz
- 8x oversampled input capture
- Line delay compensation with filtered sample point
- De-bouncing filter on oversampled input
- Variable frame format with crc check
- Command (CDS/CDM) interface
- Supports up to 100 m cable
- Runs on AM335x and AM437x with ICSS
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
Design files & products
Design files
Download ready-to-use system files to speed your design process.
TIDU794A.PDF (1572 K)
Reference design overview and verified performance test data
TIDRC79A.ZIP (1276 K)
Detailed schematic diagram for design layout and components
TIDRC80A.ZIP (580 K)
Complete listing of design components, reference designators, and manufacturers/part numbers
TIDRC78A.ZIP (6065 K)
PCB layer plot file used for generating PCB design layout
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Technical documentation
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| Type | Title | Date | ||
|---|---|---|---|---|
| * | Design guide | BiSS-C Interface Master Design Guide (Rev. A) | Feb. 08, 2016 | |
| Technical article | Designing an EMC-compliant interface to motor position encoders – Part 6 | Nov. 20, 2015 | ||
| More literature | ARM MPU with integrated BiSS C Master Interface Firmware | Feb. 23, 2015 |
Related design resources
Reference designs
REFERENCE DESIGN
Support & training
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