8-Bit Dual-Supply Bus Transceiver with Configurable Voltage-Level Shifting and 3-State Outputs
Exact equivalent in functionality and parametrics to the compared device:
Product details
Parameters
Package | Pins | Size
Features
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 8000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
- Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
- VCC Isolation Feature – If Either VCC Input Is at GND, All I/O Ports Are in the High-Impedance State
- Ioff Supports Partial Power-Down Mode Operation
- Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.4-V to 3.6-V Power-Supply Range
- I/Os Are 4.6-V Tolerant
- Maximum Data Rates
- 170 Mbps (VCCA < 1.8 V or VCCB < 1.8 V)
- 320 Mbps (VCCA ≥ 1.8 V and VCCB ≥ 1.8 V)
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Description
This 8-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVC8T245 is optimized to operate with VCCA/VCCB set at 1.4 V to 3.6 V. The device is operational with VCCA/VCCB as low as 1.2 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.
The SN74AVC8T245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are effectively isolated.
The SN74AVC8T245 is designed so that the control pins (DIR and OE) are supplied by VCCA.
The SN74AVC8T245 solution is compatible with a single-supply system and can be replaced later with a 245 function, with minimal printed circuit board redesign.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, thus preventing damaging current backflow through the device when it is powered down.
The VCC isolation feature ensures that if either VCC input is at GND, both ports are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE shall be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Technical documentation
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
Features
- Board design allows for versatility in evaluation
- Supports a wide-range of logic devices
Description
Features
- Board design allows for versatility in evaluation
- Supports a wide-range of logic and translation devices with included dual supply support
- Board has 9 sections that can be broken apart for a smaller form factor
Description
The generic EVM is designed to support one, two, four and eight channel LVC and AVC direction-controlled translation devices. It also supports the bus hold and automotive -Q1 devices in the same number of channels. The AVC are low voltage translation devices with lower drive strength of 12mA. LVC is (...)
Features
- SMB connector available for high speed operation
- Ground port available on each header pin to maintain signal integrity
- DIR and OE have 10K ohm pull up /pull down resistor options
- Designed to support up to 20 different devices
Description
The EVMK2GX (also known as "K2G") 1GHz evaluation module (EVM) enables developers to immediately start evaluating the 66AK2Gx processor family, and to accelerate the development of audio, industrial motor control, smart grid protection and other high reliability, real-time compute intensive (...)
Features
- 66AK2G12 C66x DSP+Arm Cortex-A15 processor at 1GHz
- 2-GByte DDR3L with ECC
- TPS65911A PMIC
- Audio and serial expansion headers
- Processor SDK Linux and TI-RTOS support
Design tools & simulation
Reference designs
Design files
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download TIDA-00913 BOM.pdf (72KB) -
download TIDA-00913 Assembly Drawing.pdf (554KB) -
download TIDA-00913 PCB.pdf (2813KB) -
download TIDA-00913 CAD Files.zip (5637KB) -
download TIDA-00913 Gerber.zip (1217KB)
Design files
Design files
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download SimpleLink™ CC3200-OV788 Video/Audio Streaming Over Wi-Fi BOM.pdf (216KB) -
download SimpleLink™ CC3200-OV788 Video/Audio Streaming Over Wi-Fi Assembly Files.zip (20KB) -
download SimpleLink™ CC3200-OV788 Video/Audio Streaming Over Wi-Fi PCB.pdf (117KB) -
download SimpleLink™ CC3200-OV788 Video/Audio Streaming Over Wi-Fi CAD Files.zip (554KB) -
download SimpleLink™ CC3200-OV788 Video/Audio Streaming Over Wi-Fi Gerber.zip (95KB)
Design files
Design files
Design files
Design files
-
download TIDA-00909 BOM.pdf (72KB) -
download TIDA-00909 Assembly Drawing.pdf (554KB) -
download TIDA-00909 PCB.pdf (2813KB) -
download TIDA-00909 CAD Files.zip (5846KB) -
download TIDA-00909 Gerber.zip (1218KB)
Design files
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download TIDA-00175 BOM.pdf (48KB) -
download TIDA-00175 Assembly Drawing.pdf (303KB) -
download TIDA-00175 PCB.pdf (1702KB) -
download TIDA-00175 Altium.zip (3121KB) -
download TIDA-00175 Gerber.zip (195KB)
Design files
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download TIDA-00172 BOM.pdf (209KB) -
download TIDA-00172 Assembly Drawing.pdf (130KB) -
download TIDA-00172 Altium.zip (2340KB) -
download TIDA-00172 Gerber.zip (185KB) -
download TIDA-00172 Design Calculator.zip (125KB)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
TSSOP (PW) | 24 | View options |
TVSOP (DGV) | 24 | View options |
VQFN (RHL) | 24 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Support & training
TI E2E™ forums with technical support from TI engineers
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