SN74AVC8T245

• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 8000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)
• Control Inputs V_IH/V_IL Levels Are Referenced to V_CCA Voltage
• V_CC Isolation Feature – If Either V_CC Input Is at GND, All I/O Ports Are in the High-Impedance State
• I_off Supports Partial Power-Down Mode Operation
• Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.4-V to 3.6-V Power-Supply Range
• I/Os Are 4.6-V Tolerant
• Maximum Data Rates
  • 170 Mbps (V_CCA  < 1.8 V or V_CCB  < 1.8 V)
  • 320 Mbps (V_CCA  ≥ 1.8 V and V_CCB  ≥ 1.8 V)

All trademarks are the property of their respective owners.

This 8-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVC8T245 is optimized to operate with V_CCA/V_CCB set at 1.4 V to 3.6 V. The device is operational with V_CCA/V_CCB as low as 1.2 V. The A port is designed to track V_CCA. V_CCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track V_CCB. V_CCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVC8T245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are effectively isolated.

The SN74AVC8T245 is designed so that the control pins (DIR and OE) are supplied by V_CCA.

The SN74AVC8T245 solution is compatible with a single-supply system and can be replaced later with a ’245 function, with minimal printed circuit board redesign.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, thus preventing damaging current backflow through the device when it is powered down.

The V_CC isolation feature ensures that if either V_CC input is at GND, both ports are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE shall be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.