Gigabit Ethernet link aggregator reference design


Design files


The Gigabit Ethernet Link Aggregator reference design features the TLK10081 device which is a multi-rate link aggregator intended for use in high-speed bi-directional point-to-point data transmission systems to reduce the number of physical links by multiplexing lower speed serial links into higher speed serial links. This reference design helps customers reduce the number of serial links that need to be implemented and managed within an application. TLK10081 enables customers to aggregate and de-aggregate multiple serial links, of all types including raw data types. Also, featured is the CDCM6208 device that can provide extremely low-jitter Clock input to the TLK10081 in customer systems that do not have one available (or does not meet the jitter requirement of the system). The high-speed signals of channel A have been routed to SFP+ modules for easy evaluation in systems that implement optical fiber configurations. The high-speed signals of channel B have been routed to edge launch SMA connectors for easy evaluation in systems that use standard test equipment.

  • TLK10081 has the ability to handle many different data types without the need encode the data in a special way. Some common signals include 1 GbE, SGMII, as well as raw data signals at rates from 250 Mbps to 1.25 Gbps
  • 8 × (0.25 to 1.25 Gbps) to 1 x (2 to 10 Gbps) Multiplexing
  • Supports flexible clocking schemes including externally-jitter-cleaned clock recovered from the high-speed side
  • Lowest power consumption per channel (800mW Nominal/Ch)
  • Link aggregation helps reduce cables or routing traces within a system through multiplexing lower speed serial signals into a single high speed serial link
  • Use TLK10081 for de-aggregation on the recieve side of the system
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A fully assembled board has been developed for testing and performance validation only, and is not available for sale.

Design files & products

Design files

Download ready-to-use system files to speed your design process.

TIDU272.PDF (720 K)

Test results for the reference design, including efficiency graphs, test prerequisites and more

TIDC511.ZIP (3110 K)

Detailed schematic diagram for design layout and components

TIDR880.PDF (421 K)

Detailed schematic diagram for design layout and components

TIDR881.PDF (241 K)

Complete listing of design components, reference designators, and manufacturers/part numbers


Includes TI products in the design and potential alternatives.

Other interfaces

TLK1008110-Gbps 1 to 8 channel multi-rate redundant link aggregator

Data sheet: PDF
Auto-direction voltage translators

TXB01088-Bit Bidirectional Voltage-Level Shifter with Auto Direction Sensing and +/-15-kV ESD Protect

Data sheet: PDF | HTML
Clock buffers

CDCLVP1204Low-jitter, two-input, selectable 1:4 universal-to-LVPECL buffer

Data sheet: PDF | HTML
Clock generators

CDCM62082:8 ultra-low power, low jitter clock generator

Data sheet: PDF | HTML
I2C general-purpose I/Os (GPIOs)

TCA642424-bit translating 1.65- to 5.5-V I2C/SMBus I/O expander with interrupt, reset & config registers

Data sheet: PDF
Linear & low-dropout (LDO) regulators

TLV702300-mA, high-PSRR, low-IQ, low-dropout voltage regulator with enable

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TPS744013-A, low-VIN (0.8-V), low-noise, high-PSRR, adjustable ultra-low-dropout voltage regulator

Data sheet: PDF | HTML

Technical documentation

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Type Title Date
User guide TIDA-00269 Quick Start Guide Jul. 14, 2014
Test report TIDA-00269 Test Results Jul. 14, 2014

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