Low jitter, 2-input selectable 1:4 universal-to-LVPECL buffer
Product details
Parameters
Package | Pins | Size
Features
- 2:4 Differential Buffer
- Selectable Clock Inputs Through Control Terminal
- Universal Inputs Accept LVPECL, LVDS, and
LVCMOS/LVTTL - Four LVPECL Outputs
- Maximum Clock Frequency: 2 GHz
- Maximum Core Current Consumption: 45 mA
- Very Low Additive Jitter: <100 fs, RMS in 10-kHz
to 20-MHz Offset Range:- 57 fs, RMS (typical) at 122.88 MHz
- 48 fs, RMS (typical) at 156.25 MHz
- 30 fs, RMS (typical) at 312.5 MHz
- 2.375-V to 3.6-V Device Power Supply
- Maximum Propagation Delay: 450 ps
- Maximum Output Skew: 15 ps
- LVPECL Reference Voltage, VAC_REF, Available
for Capacitive-Coupled Inputs - Industrial Temperature Range: –40°C to +85°C
- Supports 105°C PCB Temperature (Measured at
Thermal Pad) - ESD Protection Exceeds 2 kV (HBM)
Description
The CDCLVP1204 is a highly versatile, low additive jitter buffer that can generate four copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1204 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control terminal. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 15 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP1204 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to four pairs of differential LVPECL clock outputs (OUT0, OUT3) with minimum skew for clock distribution. The CDCLVP1204 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP1204 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) must be applied to the unused negative input terminal. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.
The CDCLVP1204 is characterized for operation from –40°C to +85°C.
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | CDCLVP1204 Four LVPECL Output, High-Performance Clock Buffer datasheet (Rev. F) | Sep. 03, 2015 |
User guide | CDCLVP1204 User's Guide | Jul. 09, 2009 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
The CDCLVP1204 is a high-performance, low additive phase noise clock buffer. It has two universal input buffers that support either single-ended or differential clock inputs, selectable through a control pin. The device also features on-chip bias generators that can provide the LVPECL common-mode (...)
Features
- Easy-to-use evaluation board to fan out low phase noise clocks
- Easy device setup
- Fast configuration
- Control pins configurable through jumpers
- Board powered at +2.5-/+3.3V
- Single-ended or differential input clocks
- CDCLVP1204 supports four LVPECL outputs; CDCLVP1204EVM supports two LVPECL outputs
Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
Reference designs
Design files
-
download TIDA-00352 BOM (Daughter Card).pdf (236KB) -
download TIDA-00352 BOM (Motherboard).pdf (283KB) -
download TIDA-00352 PCB (Daughter Card).pdf (1522KB) -
download TIDA-00352 PCB (Motherboard).pdf (6984KB) -
download TIDA-00352 CAD Files (Daughter Card).zip (1148KB) -
download TIDA-00352 CAD Files (Motherboard).zip (2759KB)
Design files
-
download TIDA-00309 BOM.pdf (184KB) -
download TIDA-00309 PCB.pdf (6984KB) -
download TIDA-00309 CAD Files.zip (298KB) -
download TIDA-00309 Gerber.zip (2361KB)
Design files
-
download TIDA-00269 BOM.pdf (241KB)
Design files
-
download TIDA-00234 BOM.pdf (62KB) -
download TIDA-00234 Gerber.zip (1083KB)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
VQFN (RGT) | 16 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
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Support & training
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