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Product details

Parameters

Output options Adjustable Output Iout (Max) (A) 3 Vin (Max) (V) 5.5 Vin (Min) (V) 0.8 Vout (Max) (V) 3.6 Vout (Min) (V) 0.8 Noise (uVrms) 13 Iq (Typ) (mA) 3 Thermal resistance θJA (°C/W) 27 Approx. price (US$) 2.20 | 1ku Load capacitance (Min) (µF) 0 Rating Catalog Regulated outputs (#) 1 Features Enable, Power Good, Soft Start Accuracy (%) 1 PSRR @ 100 KHz (dB) 50 Dropout voltage (Vdo) (Typ) (mV) 115 Operating temperature range (C) -40 to 125 open-in-new Find other Linear regulators (LDO)

Package | Pins | Size

TO-263 (KTW) 7 154 mm² 10.1 x 15.24 VQFN (RGR) 20 12 mm² 3.5 x 3.5 VQFN (RGW) 20 25 mm² 5 x 5 open-in-new Find other Linear regulators (LDO)

Features

  • Input Voltage Range: 1.1 V to 5.5 V
  • Soft-Start (SS) Pin Provides a Linear Startup With Ramp Time Set by External Capacitor
  • 1% Accuracy Over Line, Load, and Temperature
  • Supports Input Voltages as Low as 0.9 V With External Bias Supply
  • Adjustable Output: 0.8 V to 3.6 V
  • Ultra-Low Dropout: 115 mV at 3.0 A (typical)
  • Stable With Any or No Output Capacitor
  • Excellent Transient Response
  • Open-Drain Power-Good (VQFN Only)
  • Packages: 5-mm × 5-mm × 1-mm VQFN (RGW), 3.5-mm × 3.5-mm VQFN (RGR), and DDPAK

All trademarks are the property of their respective owners.

open-in-new Find other Linear regulators (LDO)

Description

The TPS74401 low-dropout (LDO) linear regulators provide an easy-to-use robust power-management solution for a wide variety of applications. The user-programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current on start-up. The soft-start is monotonic and well-suited for powering many different types of processors and application-specific integrated circuits (ASICs). The enable input and power-good output allow easy sequencing with external regulators. This complete flexibility lets the user configure a solution that meets the sequencing requirements of field-programmable gate arrays (FPGAs), digital signal processors (DSPs), and other applications with specific start-up requirements.

A precision reference and error amplifier deliver 1% accuracy over load, line, temperature, and process. The TPS74401 family of LDOs is stable without an output capacitor or with ceramic output capacitors. The device family is fully specified from TJ = –40°C to 125°C. The TPS74401 is offered in two 20-pin small VQFN packages (a 5-mm × 5-mm RGW and a
3.5-mm × 3.5-mm RGR package), yielding a highly compact total solution size. For applications that require additional power dissipation, the DDPAK (KTW) package is also available.

open-in-new Find other Linear regulators (LDO)
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Similar but not functionally equivalent to the compared device:
TPS7A84A ACTIVE 3-A, low-VIN (1.1-V), low-noise, high-accuracy, ultra-low-dropout voltage regulator with power good 3-A LDO with lower-noise (4.4uVrms), low dropout (200mV) and improved accuracy (0.75%) and wider VOUT range

Technical documentation

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Type Title Date
* Datasheet TPS74401 3.0-A, Ultra-LDO with Programmable Soft-Start datasheet (Rev. R) Apr. 06, 2016
Application notes Using Thermal Calculation Tools for Analog Components (Rev. A) Aug. 30, 2019
Application notes A Topical Index of TI LDO Application Notes (Rev. F) Jun. 27, 2019
Technical articles LDO basics: capacitor vs. capacitance Aug. 01, 2018
Technical articles LDO Basics: Preventing reverse current Jul. 25, 2018
Technical articles LDO basics: introduction to quiescent current Jun. 20, 2018
Selection guides Low Dropout Regulators Quick Reference Guide (Rev. P) Mar. 21, 2018
Application notes LDO Noise Demystified (Rev. A) Aug. 09, 2017
Application notes LDO PSRR Measurement Simplified (Rev. A) Aug. 09, 2017
Technical articles LDO basics: noise – part 1 Jun. 14, 2017
Selection guides Power Management for Xilinx FPGAs Feb. 04, 2014
Application notes 4Q 2012 Issue Analog Applications Journal Sep. 25, 2012
Application notes LDO noise examined in detail Sep. 25, 2012
Application notes Power Solution Using Discrete DC/DC Converters and LDOs (Rev. B) Aug. 26, 2010
Application notes Power Ref Design for TMS320C6472, 12-Vin Digital Pwr Cntrlrs, and LDOs (Rev. A) May 24, 2010
Application notes Pwr Ref Design f/'C6472 12-Vin Digital Pwr Controllers and LDOs Apr. 28, 2010
Application notes 'C6472 12Vin Flexible Pwr Design Using DCDC Controllers and LDOs (8x C6472) Mar. 26, 2010
Application notes Using New Thermal Metrics Dec. 15, 2009
Application notes A 3-A, 1.2-Vout linear regulator with 80% efficiency and Plost < 1W Oct. 10, 2006
User guides TPS74x01EVM-118 User's Guide Jun. 20, 2006

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
Description

The DAC38RF80EVM is the circuit board for evaluating DAC38RF80/84/90 digital-to-analog converters (DACs). The EVM can be used to evaluate the performance of the DAC up to 9-GSPS sampling rate. It is designed to work with the FPGA-based pattern generator card TSW14J56EVM (Rev B and up). The available (...)

Features
  • Allows evaluation of DAC38RF80/84/90 up to 9-GSPS sampling rate
  • Supports up to 12.5-Gbps SerDes signaling rate across FMC
  • Two on-chip PLLs with superior phase noise to simplify system clock generation; also supports external clock mode
  • AC-coupled output with 2:1 impedance transformer for (...)
EVALUATION BOARDS Download
document-generic User guide
Description
The DAC38RF82EVM is the circuit board for evaluating DAC38RF82/83/85/93 digital to analog converters (DACs). The EVM can be used to evaluate the performance of the DAC up to 9GSPS sampling rate and it is designed to work with the TSW14J56 EVM. The available FMC connector also makes it possible to (...)
Features
  • Allows evaluation of DAC38RF82/83/85/93 up to 9GSPS sampling rate
  • Supports up to 12.5Gbps serdes signaling rate across FMC
  • Integrated low phase noise On–chip PLL with 2 VCOs to simplify system clock generation. Also supports external clock mode.
  • AC coupled, differential output with on-board 2:1 (...)
EVALUATION BOARDS Download
document-generic User guide
Description
The DAC38RF86 evaluation module (EVM) is the circuit board for evaluating DAC38RF86 digital-to-analog converters (DACs). The EVM can be used to evaluate the performance of the DAC up to 9-GSPS sampling rate and is designed to work with the TSW14J56EVM (Rev B and up). The available FMC connector also (...)
Features
  • Allows evaluation of DAC38RF86 or DAC38RF96 up to 9-GSPS sampling rate
  • Supports up to 12.5-Gbps SerDes signaling rate across FMC
  • Two on-chip PLLs with superior phase noise to simplify system clock generation; also supports external clock mode
  • AC-coupled output with integrated impedance transformer (...)
EVALUATION BOARDS Download
document-generic User guide
Description
The DAC38RF87 evaluation module (EVM) is the circuit board for evaluating the DAC38RF87 digital-to-analog converter (DAC). The EVM can be used to evaluate the performance of the DAC up to 9-GSPS sampling rate and is designed to work with the TSW14J56EVM (Rev B and up). The available FMC connector (...)
Features
  • Allows evaluation of DAC38RF87/97 up to 9-GSPS sampling rate
  • Supports up to 12.5-Gbps SerDes signaling rate across FMC
  • Two on-chip PLLs with superior phase noise to simplify system clock generation; also supports external clock mode
  • AC-coupled output with integrated impedance transformer (DAC38RF87) for (...)
EVALUATION BOARDS Download
document-generic User guide
Description

The DAC38RF89 evaluation module (EVM) is the circuit board for evaluating DAC38RF89 digital-to-analog converters (DACs). The DAC38RFEVM can be used to evaluate the performance of the DAC up to 9-GSPS sampling rate and is designed to work with the TSW14J56EVM (Rev B and up). The available FMC (...)

Features
  • Allows evaluation of DAC38RF89 up to 9-GSPS sampling rate
  • Supports up to 12.5-Gbps SerDes signaling rate across FMC
  • Two on-chip PLLs with superior phase noise to simplify system clock generation; also supports external clock mode
  • AC-coupled output with integrated impedance transformer (DAC38RF89) for (...)
EVALUATION BOARDS Download
TPS74401 Evaluation Module
TPS74401EVM-118
document-generic User guide
$10.00
Description

The TPS74401EVM-118 evaluation module (EVM) is designed to help the user easily evaluate and test the operation and functionality of the TPS74401 LDO linear regulator. The EVM uses the TPS74401, 3 A linear regulator with programmable soft-start and integrated power good (PG). Refer to (...)

Features
  • Supports input voltages as low as 0.9 V with external bias supply due to ultra-low dropout
  • Adjustable output (0.8 V to 3.6 V) up to 3 A
  • Soft-start time set by external capacitor
  • Stable with any or no output capacitor
  • 1% accuracy over line, load and temperature
  • Open drain power good (PG)
  • 5 mm x 5 mm (...)

Design tools & simulation

SIMULATION MODELS Download
SBVM619.ZIP (3 KB) - PSpice Model
SIMULATION MODELS Download
SLIM008B.ZIP (63 KB) - PSpice Model
SIMULATION MODELS Download
SLIM009.TSC (89 KB) - TINA-TI Reference Design
SIMULATION MODELS Download
SLIM010.TSC (120 KB) - TINA-TI Reference Design
SIMULATION MODELS Download
SLIM011.ZIP (35 KB) - TINA-TI Spice Model
SCHEMATICS Download
SLVR303A.PDF (196 KB)
SCHEMATICS Download
SLVR306.PDF (92 KB)
SCHEMATICS Download
SLVR354.PDF (150 KB)
SCHEMATICS Download
SLVR355.PDF (141 KB)
SCHEMATICS Download
SLVR356.PDF (193 KB)

Reference designs

REFERENCE DESIGNS Download
Power Supply Reference Design for Optimizing Spur and Phase Noise in RF-sampling DACs
TIDA-01215 — This reference design provides an efficient power supply scheme to power-up the RF-sampling DAC38RF8x digital-to-analog data converter (DAC) without sacrificing performance and also reduces board area and BOM. The reference design uses both DC/DC switchers and an LDO to power-up the DAC38RF8x while (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
RF-Sampling S-Band Radar Transmitter Reference Design
TIDA-01240 — Synthesis of waveforms appropriate for an S-band multifunction phased array radar (MPAR) is demonstrated with an RF sampling architecture utilizing the DAC38RF80, a 9GSPS 16-bit digital-to-analog converter (DAC). The RF sampling transmit architecture simplifies the signal chain, bringing the data (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Current-Sharing Dual LDOs
TIDA-00270 This power supply topology is capable of sourcing 6A via two LDOs operating in parallel. The solution sources current evenly between the two TPS74401’s, each capable of supplying 3A. This design allows for higher currents to be supplied than is typically possible with a single LDO. It also (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Continuous Wave Phase-aligned Multitone Generator: DC-to-6-GHz RF-Sampling DAC Reference Design
TIDA-01084 The TIDA-01084 reference design demonstrates the use of RF sampling DAC to generate continuous phase-aligned multitone waveforms. With four 48-bit independent NCOs, the 14-bit, 9GSPS DAC38RF83 can generate four CW tones placed anywhere within the first Nyquist zone or up to 6 GHz in the second.

This (...)

document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
SDI Video Aggregation Reference Design
TIDA-00352 This verified reference design is a complete four channel SDI aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous HD-SDI sources together into one 5.94 Gbps serial link. The serial data is transferred via copper or optical fiber where a second TLK10022 is used (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
DisplayPort Video 4:1 Aggregation Reference Design
TIDA-00309 This verified reference design is a complete four channel DisplayPort aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous DisplayPort (DP) sources together into one 10.8 Gbps serial link. The serial data is transferred via copper or optical fiber where a (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Gigabit Ethernet Link Aggregator Reference Design
TIDA-00269 The Gigabit Ethernet Link Aggregator reference design features the TLK10081 device which is a multi-rate link aggregator intended for use in high-speed bi-directional point-to-point data transmission systems to reduce the number of physical links by multiplexing lower speed serial links into higher (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Dual-channel XAUI to SFI Reference Design for Systems with Two or More SFP+ Optical Ports
TIDA-00234 The TIDA-00234 XAUI to SFI reference design is intended for Enterprise and Service Provider Networking applications like Ethernet Switches and Routers that implement multiple 10G Ethernet compliant Optical (SFP+) ports. This reference design features the TLK10232 device which is the most compact (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
FPGA Firmware Example of How To Interface Altera FPGAs to High-Speed LVDS-Interface Data Converters
TIDA-00069 This reference design and the associated example Verilog code can be used as a starting point for interfacing Altera FPGAs to Texas Instruments' high-speed LVDS-interface analog-to-digital converters (ADC) and digital-to-analog converters (DAC). The firmware implementation is explained and the (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
DDPAK/TO-263 (KTW) 7 View options
VQFN (RGR) 20 View options
VQFN (RGW) 20 View options

Ordering & quality

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