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Product details

Parameters

Operating temperature range (C) -40 to 85 open-in-new Find other Other interfaces

Package | Pins | Size

FCBGA (CTR) 144 169 mm² 13 x 13 open-in-new Find other Other interfaces

Features

  • Automatic Digital Multiplexing/De-Multiplexing of 1 to 8
    Independent Lower Speed Gigabit Serial Lines into a Single
    Higher Speed Gigabit Serial Line with Extensive Media
    Transmission Capabilities.
  • 1∼8 × (0.25 to 1.25 Gbps) to 1 x (2 to 10 Gbps) Multiplexing
  • 1 × (0.5 to 2.5 Gbps) to 1 × (0.5 to 2.5 Gbps)
  • Dynamic Port Aggregation Supported
  • Programmable High Speed Redundant Switching
  • Wide Data Rate Range for Multiple Application Support
  • Transmit De-Emphasis and Adaptive Receiver Equalization on
    Both Low Speed and High Speed Sides
  • MDIO Clause 22 control interface
  • 8B/10B ENDEC Coding Support
  • Raw (Unencoded) Data Support
  • Core Supply 1V; I/O: 1.5V/1.8V
  • Superior Signal Integrity Performance
  • Low Power Operation: < 800 mW per channel (typ)
  • Rate Matching Support (For compatible data protocols like GE PCS)
  • Full Non-Blocking Receiver Crosspoint Mapping Capability
  • Flexible Clocking
  • Multi Drive Capability (SFP+, backplane, cable)
  • Support for Programmable High Speed Lane Alignment Characters
  • Support for Programmable HS/LS 10-Bit Alignment Characters
  • Wide Range of Built-in Test Patterns
  • 144-pin, 13mmx13mm FCBGA Package
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Description

The TLK10081 is a multi-rate link aggregator intended for use in high-speed bi-directional point-to-point data transmission systems. The device allows for a reduction in the number of physical links required for a certain data throughput by multiplexing multiple lower-rate serial links into higher-rate serial links.

The TLK10081 has a low-speed interface which can accommodate one to eight bidirectional serial links running at rates from 250 Mbps to 1.25 Gbps (maximum of 10 Gbps total throughput). The device’s high speed interfaces can operate at rates from 1 Gbps to 10 Gbps. The high speed interface is designed to run at 8 x the low speed serial rate regardless of the number of lanes connected. Filler data will be placed on any unused lanes in order to keep the interleaved lane ordering constant. This allows for low speed lanes to be hot swapped during normal operation without requiring a change in configuration.

A 1:1 mode is also supported for data rates ranging from 0.5 Gbps to 2.5 Gbps, whereby both low speed and high speed are rate matched. The TX and RX datapaths are also independent, so TX may operate in 8:1 mode while RX operates in 1:1 mode. This independence is restricted to using the same low speed line rate. For example, the TX can operate at 8 × 1.25 Gbps while RX operates at 1 × 1.25 Gbps.

The individual Low Speed lanes may also operate at independent rates in byte interleave mode, provided they are operating at integer multiples. The High Speed line rate must be configured based on the fastest Low Speed line rate.

The device has multiple interleaving/de-interleaving schemes that may be used depending on the data type. These schemes allow for the low speed lane ordering to be recovered after the lanes are transmitted over a single high-speed link. There is also a programmable scrambling/de-scrambling function available to help ensure that the high-speed data has suitable properties for transmission (i.e., sufficient transition density for clock recovery and DC balance over time) even for non-ideal input data.

The TLK10081 has the ability to perform lane alignment on 2, 3, or 4 lanes with up to four bytes of lane de-skew.

Both the low speed and high speed side interfaces (transmitters and receivers) use CML signaling with integrated termination resistors and feature programmable transmitter de-emphasis levels and adaptive receive equalization to help compensate for media impairments at higher frequencies. The device’s serial transceivers used are capable of interfacing to optical modules as well as higher-loss connections such as PCB backplanes and controlled-impedance copper cabling.

To aid in system synchronization, the TLK10081 is capable of extracting clocking information from the serial input data streams and outputting a recovered clock signal. This recovered clock can be input to a jitter cleaner in order to provide a synchronized system clock. The device also has two reference clock input ports and a flexible internal PLL, allowing for various serial rates to be supported with a single reference clock input frequency.

The device has various built-in self-test features to aid with system validation and debugging. Among these are pattern generation and verification on all serial lanes as well as internal data loopback paths.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 7
Type Title Date
* Datasheet 10Gbps 1-8 Channel Multi-Rate Serial Link Aggregator datasheet Nov. 08, 2013
Technical articles Get Connected: Data aggregation using a general purpose SerDes Dec. 17, 2014
Application note Video Aggregation HD-SDI Interface Application Sheet Oct. 01, 2014
Technical articles How to design your system like a true pirate engineer Sep. 19, 2014
Application note Link Aggregation Interface Application Sheet Jan. 10, 2014
User guide TLK10022 and TLK10081 EVM User's Guide Nov. 08, 2013
User guide TLK10022 and TLK10081 Multi-Rate Lane Aggregator EVM GUI User's Guide Nov. 08, 2013

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
2999
Description

This motherboard evaluation board for TLK10081 comes with custom-developed GUI and a detailed EVM user guide. The EVM along with the GUI, enable customers to configure the registers of all the channels independently and to debug the device. The user’s guide provides guidance on proper use of (...)

Features
  • Supports evaluation of high-speed signals, which are accessible via SMA connectors or an optionally-installed optical module  
  •  MDIO interface easily controlled via USB port using a graphical user interface
  •  Runs from a single 5V power supply
  •  Voltage monitoring circuits with LED indicators ease (...)

Software development

GUI FOR EVALUATION MODULE (EVM) Download
SLLC440.ZIP (37141 KB)

Design tools & simulation

SIMULATION MODEL Download
SLLM233.ZIP (9164 KB) - HSpice Model
SIMULATION MODEL Download
SLLM234.ZIP (60 KB) - IBIS Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SIMULATION TOOL Download
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)

Reference designs

REFERENCE DESIGNS Download
Gigabit Ethernet link aggregator reference design
TIDA-00269 The Gigabit Ethernet Link Aggregator reference design features the TLK10081 device which is a multi-rate link aggregator intended for use in high-speed bi-directional point-to-point data transmission systems to reduce the number of physical links by multiplexing lower speed serial links into higher (...)
document-generic Schematic

CAD/CAE symbols

Package Pins Download
FCBGA (CTR) 144 View options

Ordering & quality

Information included:
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  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

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