Multi-channel RF transceiver, low-noise clocking reference design for radar and EW applications


Design files


In modern radar and electronic warfare (EW) systems, active electronically-scanned array (AESA) antenna systems are often used with high speed multi-channel RF transceivers. These systems require very low noise clocking capable of precise channel-to-channel skew adjustment to achieve the optimal system performance like signal-to-noise ratio (SNR), spurious-free dynamic range (SFDR), IMD3 and effective number of bits (ENOB). This reference design demonstrates LMX2820- and LMK04832-based low-noise JESD204B-compliant clocks and provide to multiple AFE7950s up to X-band operation and synchronized them < 10 ps with improved system performance at 9-GSPS/3-GSPS DAC/ADC clocks.

  • Multi-channel and scalable JESD204B-compliant clock
  • Low-phase noise clocking for RF sampling AFEs
  • Configurable phase synchronization to achieve low skew in multi-channel systems
  • Low noise and low ripple DC/DC achieves equivalent performance to LDO with improved efficiency
  • Demonstrates 8T8R synchronized RF sampling transceiver
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A fully assembled board has been developed for testing and performance validation only, and is not available for sale.

Design files & products

Design files

Download ready-to-use system files to speed your design process.

TIDUEZ6.PDF (1385 K)

Reference design overview and verified performance test data

TIDM970.ZIP (2292 K)

Detailed schematic diagram for design layout and components

TIDM971.ZIP (455 K)

Complete listing of design components, reference designators, and manufacturers/part numbers

TIDM972.PDF (1610 K)

Detailed overview of design layout for component placement

TIDM973.ZIP (12926 K)

Files used for 3D models or 2D drawings of IC components

TIDCG31.ZIP (1784 K)

Design file that contains information on physical board layer of design PCB


Includes TI products in the design and potential alternatives.

RF PLLs & synthesizers

LMX282022.6-GHz wideband RF synthesizer with phase synchronization, JESD and <5-µs frequency calibration

Data sheet: PDF | HTML
Buck converters (integrated switch)

TPS6291317-VIN, 3-A low-noise and low-ripple buck converter with integrated ferrite bead filter compensation

Data sheet: PDF | HTML
Clock buffers

LMK1C11044-channel output LVCMOS 1.8-V buffer

Data sheet: PDF | HTML
Clock jitter cleaners & synchronizers

LMK04832Ultra-low-noise, 3.2-GHz, 15-output, JESD204B clock jitter cleaner with dual loop

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TPS7A533-A, low-VIN (1.1 V) low-noise high-accuracy ultra-low-dropout (LDO) voltage regulator

Data sheet: PDF | HTML
RF-sampling transceivers

AFE79004-transmit, 6-receive RF-sampling transceiver, 5-MHz to 7.4-GHz, max 1200-MHz IBW

Data sheet: PDF | HTML
RF-sampling transceivers

AFE79504-transmit, 6-receive RF-sampling transceiver, 600-MHz to 12-GHz, max 1200-MHz IBW

Data sheet: PDF | HTML

Technical documentation

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Type Title Date
* Design guide Multichannel RF Transceiver Low-Noise Clocking Ref. Des. for Radar and EW Applic PDF | HTML Dec. 16, 2021
Application note LMX2820 RF Synthesizer Phase Noise Improvement With Alternative Topologies (Rev. A) PDF | HTML May 22, 2023
Application note Combining Two LMX2820 Synthesizer Outputs for Improved Phase Noise (Rev. A) PDF | HTML Mar. 03, 2022

Related design resources

Hardware development

AFE7950EVM AFE7950 evaluation module for four-transmit, six-receive, X-band, RF-sampling AFE

Reference designs

TIDA-010131 Multichannel RF transceiver clocking reference design for RADARs and wireless 5G testers

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