Multichannel RF transceiver clocking reference design for RADARs and wireless 5G testers


Design files


Analog front end for high-speed end equipments like phased-array radars, wireless communication testers, and electronic warfare require synchronized, multipletransceiver signal chains. Each transceiver signal chain includes high-speed, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and a clock subsystem. The clock subsystem provides low noise sampling clocks with precise delay adjustment to achieve lowest channel-to-channel skew and optimum system performance like signal-to-noise ratio (SNR), spurious free dynamic range (SFDR), IMD3, effective number of bits (ENOB), and so forth. This reference design demonstrates multichannel JESD204B clocks generation and system performance with AFE7444 EVMs. Channel-to-channel skew better than 10 ps achieved with 6 GSPS/3 GSPS DAC/ADC clocks up to 2.6-GHz radio frequencies and system performance like SNR and SFDR are comparable to the AFE7444 data sheet specifications.

  • JESD204B complaint clock solution for 8T8R RF sampling analog front end
  • Digital functions synchronization across multiple RF AFE transceivers
  • Low phase noise clock generation for 14-bit, RF sampling AFEs
  • Fine phase delay adjustment in steps of approximately 500 fs to achieve phase synchronization across multiple devices
  • Supports high-speed data converters and capture cards (AFE7444EVM, TSW14J56EVM, TSW14J57EVM)
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A fully assembled board has been developed for testing and performance validation only, and is not available for sale.

Design files & products

Design files

Download ready-to-use system files to speed your design process.

TIDUEK4.PDF (7788 K)

Reference design overview and verified performance test data

TIDRZ30.ZIP (2263 K)

Detailed schematic diagram for design layout and components

TIDRZ31.ZIP (314 K)

Complete listing of design components, reference designators, and manufacturers/part numbers

TIDRZ32.ZIP (882 K)

Detailed overview of design layout for component placement

TIDRZ34.ZIP (19873 K)

Files used for 3D models or 2D drawings of IC components

TIDCFB2.ZIP (2572 K)

Design file that contains information on physical board layer of design PCB

TIDRZ33.ZIP (8507 K)

PCB layer plot file used for generating PCB design layout


Includes TI products in the design and potential alternatives.

AND gates

SN74LVC1G081-ch, 2-input 1.65-V to 5.5-V 32 mA drive strength AND gate

Data sheet: PDF
Analog switches & muxes

SN74LVC2G535-V, 2:1 (SPDT), 1-channel general-purpose analog switch (available in the NanoFree™ package)

Data sheet: PDF | HTML
Analog switches & muxes

TMUX15745-V, 2:1 (SPDT), 4-channel analog switch with powered-off protection & 1.8-V input logic

Data sheet: PDF | HTML
Buck converters (integrated switch)

TPS543182.95V to 6V Input, 3A Synchronous Step-Down SWIFT™ Converter

Data sheet: PDF | HTML
Clock buffers

LMK003043.1-GHz differential clock buffer/level translator with 4 configurable outputs

Data sheet: PDF | HTML
Clock jitter cleaners & synchronizers

LMK04828Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.

Data sheet: PDF | HTML
Digital temperature sensors

LM95233±2°C Dual Remote and Local Temperature Sensor with TruTherm Technology and SMBus Interface

Data sheet: PDF

DS90LV028AQ-Q1Automotive LVDS dual differential line receiver

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TLV702300-mA, high-PSRR, low-IQ, low-dropout voltage regulator with enable

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TPS7A471-A, 36-V, low-noise, high-PSRR, low-dropout voltage regulator with enable

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TPS7A83002-A, low-VIN, low-2-A, low-VIN, low-noise, ultra-low-dropout voltage regulator with power good wi

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TPS7A90500-mA, low-noise, high-PSRR, adjustable ultra-low-dropout voltage regulator with high-accuracy

Data sheet: PDF | HTML
N-channel MOSFETs

CSD15571Q220-V, N channel NexFET™ power MOSFET, single SON 2 mm x 2 mm, 19.2 mOhm

Data sheet: PDF

LMK61E2156.250-MHz, ±50 ppm, ultra-low jitter, integrated EEPROM, fully programmable oscillator

Data sheet: PDF | HTML
RF PLLs & synthesizers

LMX259415-GHz wideband PLLatinum™ RF synthesizer with phase synchronization and JESD204B support

Data sheet: PDF | HTML
RF-sampling transceivers

AFE74444-transmit, 4-receive RF-sampling transceiver, 10-MHz to 6-GHz, max 600-MHz IBW

Data sheet: PDF | HTML
eFuses & hot swap controllers

TPS259254.5-V to 5.5-V, 30mΩ, 2-5A eFuse

Data sheet: PDF | HTML

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Technical documentation

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Type Title Date
* Design guide Multichannel RF transceiver clocking reference design for RADARs and wireless 5G Feb. 27, 2019

Related design resources

Hardware development

AFE7444EVM AFE7444 quad-channel RF-sampling AFE with 14-bit 9-GSPS DAC and 3-GSPS ADC evaluation module TSW14J57EVM Data capture/pattern generator: data converter EVM with 16 JESD204B lanes from 1.6-15Gbps

Reference designs

TIDA-010132 Multichannel RF transceiver reference design for radar and electronic warfare applications TIDA-01021 Multi-channel JESD204B 15-GHz clocking reference design for DSO, radar and 5G wireless testers TIDA-01023 High Channel Count JESD204B Clock Generation Reference Design for RADAR and 5G Wireless Testers TIDA-01024 High Channel Count JESD204B Daisy Chain Clock Reference Design for RADAR and 5G Wireless Testers

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