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LMK1C1104

ACTIVE

4-channel output LVCMOS 1.8-V buffer

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Data sheet

LMK1C1104

ACTIVE
Data sheet Order now

Product details

Function Clock buffer, Level translator, Single-ended Additive RMS jitter (typ) (fs) 19.2 Output frequency (max) (MHz) 250 Number of outputs 4 Output supply voltage (V) 1.8, 2.5, 3.3 Core supply voltage (V) 1.8, 2.5, 3.3 Output skew (ps) 25 Features 1:4 fanout, Synchronous output enable Operating temperature range (°C) -40 to 125 Rating Catalog Output type LVCMOS Input type LVCMOS
Function Clock buffer, Level translator, Single-ended Additive RMS jitter (typ) (fs) 19.2 Output frequency (max) (MHz) 250 Number of outputs 4 Output supply voltage (V) 1.8, 2.5, 3.3 Core supply voltage (V) 1.8, 2.5, 3.3 Output skew (ps) 25 Features 1:4 fanout, Synchronous output enable Operating temperature range (°C) -40 to 125 Rating Catalog Output type LVCMOS Input type LVCMOS
TSSOP (PW) 8 19.2 mm² 3 x 6.4 WSON (DQF) 8 4 mm² 2 x 2
  • High-performance 1:2, 1:3 or 1:4 LVCMOS clock buffer
  • Very low output skew < 50 ps
  • Extremely low additive jitter < 50 fs maximum
    • 7.5 fs typical at VDD = 3.3 V
    • 10 fs typical at VDD = 2.5 V
    • 19.2 fs typical at VDD = 1.8 V
  • Very low propagation delay < 3 ns
  • Synchronous output enable
  • Supply voltage: 3.3 V, 2.5 V, or 1.8 V
    • 3.3-V tolerant input at all supply voltages
    • Fail-safe inputs
  • fmax = 250 MHz for 3.3 V fmax = 200 MHz for 2.5 V and 1.8 V
  • Operating temperature range: –40°C to 125°C
  • Available in 8-pin TSSOP package
  • Available in 8-pin WSON package
  • High-performance 1:2, 1:3 or 1:4 LVCMOS clock buffer
  • Very low output skew < 50 ps
  • Extremely low additive jitter < 50 fs maximum
    • 7.5 fs typical at VDD = 3.3 V
    • 10 fs typical at VDD = 2.5 V
    • 19.2 fs typical at VDD = 1.8 V
  • Very low propagation delay < 3 ns
  • Synchronous output enable
  • Supply voltage: 3.3 V, 2.5 V, or 1.8 V
    • 3.3-V tolerant input at all supply voltages
    • Fail-safe inputs
  • fmax = 250 MHz for 3.3 V fmax = 200 MHz for 2.5 V and 1.8 V
  • Operating temperature range: –40°C to 125°C
  • Available in 8-pin TSSOP package
  • Available in 8-pin WSON package

The LMK1C110x is a modular, high-performance, low-skew, general-purpose clock buffer family from Texas Instruments. The entire family is designed with a modular approach in mind. Three different fan-out variations, 1:2, 1:3, 1:4, are available.

All of the devices within this family are pin-compatible to each other and backwards compatible to the CDCLVC110x family for easy handling.

All family members share the same high performing characteristics such as low additive jitter, low skew, and wide operating temperature range.

The LMK1C110x supports a synchronous output enable control (1G) which switches the outputs into a low state when 1G is low. These devices have a fail-safe input that prevents oscillation at the outputs in the absence of an input signal and allows for input signals before VDD is supplied.

The LMK1C110x family operates in a 1.8-V, 2.5-V and 3.3-V environment and are characterized for operation from –40°C to 125°C.

The LMK1C110x is a modular, high-performance, low-skew, general-purpose clock buffer family from Texas Instruments. The entire family is designed with a modular approach in mind. Three different fan-out variations, 1:2, 1:3, 1:4, are available.

All of the devices within this family are pin-compatible to each other and backwards compatible to the CDCLVC110x family for easy handling.

All family members share the same high performing characteristics such as low additive jitter, low skew, and wide operating temperature range.

The LMK1C110x supports a synchronous output enable control (1G) which switches the outputs into a low state when 1G is low. These devices have a fail-safe input that prevents oscillation at the outputs in the absence of an input signal and allows for input signals before VDD is supplied.

The LMK1C110x family operates in a 1.8-V, 2.5-V and 3.3-V environment and are characterized for operation from –40°C to 125°C.
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Technical documentation

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Type Title Date
* Data sheet LMK1C110x 1.8-V, 2.5-V, and 3.3-V LVCMOS Clock Buffer Family datasheet (Rev. D) PDF | HTML 18 Feb 2022
EVM User's guide LMK1C1104DQF Low-Additive, Phase-Noise LVCMOS Clock Buffer Evaluation Board PDF | HTML 16 Jun 2021
User guide LMK1C1104 Low-Additive, Phase-Noise LVCMOS Clock Buffer Evaluation Board (Rev. A) PDF | HTML 10 Dec 2020
Application note Clocking for Medical Ultrasound Systems (Rev. A) PDF | HTML 30 Sep 2020
Application note LMK1C110x Key Performance in System Level (Rev. A) 10 Mar 2020

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMK1C1104EVM — LMK1C1104 low jitter 1:4 LVCMOS fan-out buffer evaluation module

LMK1C1104 is a high-performance, low additive jitter LVCMOS clock buffer with one LVCMOS input, four LVCMOS outputs, and a global output enable pin. This evaluation module (EVM) is designed to demonstrate the electrical performance of the LMK1C1104, however, this EVM can also be used to evaluate (...)
User guide: PDF | HTML
Not available on TI.com
Evaluation board

LMK1C1108EVM — LMK1C1108 low jitter 1:8 LVCMOS fan-out buffer evaluation module

LMK1C1108 is a high-performance, low additive jitter LVCMOS clock buffer with one LVCMOS input, eight LVCMOS outputs, and a global output enable pin. This evaluation module (EVM) is designed to demonstrate the electrical performance of the LMK1C1108. This EVM can also be used to evaluate other (...)
User guide: PDF | HTML
Not available on TI.com
Simulation model

LMK1C1104 IBIS Model

SNAM234.ZIP (45 KB) - IBIS Model
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CAD/CAE symbol

LMK1C1104EVM Altium Database

SNAR039.ZIP (498 KB)
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Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Reference designs

TIDA-010230 — Multi-channel RF transceiver, low-noise clocking reference design for radar and EW applications

In modern radar and electronic warfare (EW) systems, active electronically-scanned array (AESA) antenna systems are often used with high speed multi-channel RF transceivers. These systems require very low noise clocking capable of precise channel-to-channel skew adjustment to achieve the optimal (...)
Design guide: PDF
Package Pins Download
TSSOP (PW) 8 View options
WSON (DQF) 8 View options

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