This reference design implements an 8-port IO-link master using four TIOM2212 IO-link master transceivers with TPS274C65 power switches, valuable across TI processors (MSPM0G3507, AM261x, AM243x) by an 80-pin BoosterPack™ interface. This reference design uses three port tiers (high, medium, and low-cost) to showcase how the TIOM2212 scales from full-featured to cost-optimized applications. The design also supports IO-Link COM3 at a 400μs minimum cycle time. This reference design supports 2A output on L+ and CQ, also enabling a 1A digital output with digital input function on pin 2.
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
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Reference design overview and verified performance test data
Detailed overview of design layout for component placement
Complete listing of design components, reference designators, and manufacturers/part numbers
Files used for 3D models or 2D drawings of IC components
Design file that contains information on physical board layer of design PCB
PCB layer plot file used for generating PCB design layout
Detailed schematic diagram for design layout and components
Includes TI products in the design and potential alternatives.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Design guide | TIDA-011034 High-Performance IO-Link Master Module Reference Design | PDF | HTML | Oct 28, 2026 |
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