Flexible Interface (PRU-ICSS) Reference Design for Simultaneous, Coherent DAQ Using Multiple ADCs


Design files


This reference design showcases an interface implementation for connecting multiple high voltage bipolar input, 8-channel, mux-input SAR ADCs (6) with the Sitara Arm processors for expanding the number of input channels using Programmable Real-time Unit (PRU-ICSS). ADCs are configured for simultaneous sampling of the same channels across all ADCs. The design highlights the capability of PRU-ICSS to handle 1536ksps (each sample = 16 bits) data rate by sampling 640 samples per line cycle. For 50Hz cycle, this corresponds to 32ksps per channel across 6 ADCs simultaneously (640 samples/cycle*50Hz*6 ADCs*8 Ch = 1536ksps). Also, the second PRU is used to post process the data to achieve coherent sampling.

  • Flexible interface using PRU-ICSS (Sitara Processor) for communicating with multiple SAR ADCs
  • AC voltage and current measurement accuracy:
    • AC Voltage: <±0.2% for 2.5V to 120V
    • AC Current: <±0.2% for 2.5A to 70A
    • Simultaneous sampling across six ADCs (16-bit, 500ksps/ADC)
  • PRU-ICSS Interface:
    • Programmable real-time unitiIndustrial communication subsystem (PRU-ICSS) offers flexible data capture for channel expansion
    • Firmware-based approach allows for reuse across different Sitara processors
    • Coherent sampling is achieved by computing line cycle in software and by adjusting CS signal
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Design files & products

Design files

Download ready-to-use system files to speed your design process.


Reference design overview and verified performance test data

TIDRV10.ZIP (1659 K)

Detailed schematic diagram for design layout and components

TIDRV11A.ZIP (287 K)

Complete listing of design components, reference designators, and manufacturers/part numbers

TIDRV12.ZIP (733 K)

Detailed overview of design layout for component placement

TIDRV14.ZIP (5446 K)

Files used for 3D models or 2D drawings of IC components

TIDCEC7.ZIP (7628 K)

Design file that contains information on physical board layer of design PCB

TIDRV13.ZIP (4674 K)

PCB layer plot file used for generating PCB design layout


Includes TI products in the design and potential alternatives.

Arm-based processors

AM3356Sitara processor: Arm Cortex-A8, PRU-ICSS, CAN

Data sheet: PDF | HTML
Arm-based processors

AM3357Sitara processor: Arm Cortex-A8, EtherCAT, PRU-ICSS, CAN

Data sheet: PDF | HTML
Arm-based processors

AM3358Sitara processor: Arm Cortex-A8, 3D graphics, PRU-ICSS, CAN

Data sheet: PDF | HTML
Arm-based processors

AM3359Sitara processor: Arm Cortex-A8, EtherCAT, 3D, PRU-ICSS, CAN

Data sheet: PDF | HTML
Clock buffers

CDCLVC1106Low jitter, 1:6 LVCMOS fan-out clock buffer

Data sheet: PDF | HTML
Fixed-direction voltage translators

SN74LV1T04Single Power Supply INVERTER Gate logic level shifter

Data sheet: PDF | HTML
LCD & OLED display power & drivers

TPS65131Split-Rail Converter with Dual, Positive and Negative Outputs (750mA typ)

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

LP2992250-mA, 16-V, low-dropout voltage regulator with enable

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TPS7A39150-mA, 33-V, low-noise, high-PSRR, dual-channel positive & negative low-dropout voltage regulator

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TPS7A65-Q1Automotive 300-mA, off-battery (40-V), low-IQ, low-dropout voltage regulator

Data sheet: PDF | HTML
Load switches

TPS229145.5-V, 2-A, 37-mΩ load switch

Data sheet: PDF | HTML
Noninverting buffers & drivers

SN74LVC1G17Single 1.65-V to 5.5-V buffer with Schmitt-Trigger inputs

Data sheet: PDF | HTML
Precision ADCs

ADS868816-bit, 500-kSPS, 8-channel, single-supply SAR ADC with bipolar input ranges

Data sheet: PDF | HTML
Precision op amps (Vos<1mV)

OPA4197Quad, 36-V, precision, rail-to-rail input output, low offset voltage op amp

Data sheet: PDF | HTML

Technical documentation

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Type Title Date
* Design guide Flexible Interface (PRU-ICSS) Reference Design for Simultaneous, Coherent DAQ (Rev. A) Jan. 03, 2019
Technical article Improving sensor DAQ performance using the PRU-ICSS for grid protection and contro PDF | HTML Oct. 09, 2018
Technical article Interfacing multiple ADCs to a single processor for grid protection and control PDF | HTML Sep. 13, 2018
Application note HSR/PRP Solutions on Sitara Processors for Grid Substation Communication Apr. 17, 2018
Technical article Analog interfacing for grid infrastructure with Sitara processors PDF | HTML Feb. 15, 2018

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