Flexible Interface (PRU-ICSS) Reference Design for Simultaneous, Coherent DAQ Using Multiple ADCs
TIDA-01555
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Key Document
Description
This reference design showcases an interface implementation for connecting multiple high voltage bipolar input, 8-channel, mux-input SAR ADCs (6) with the Sitara Arm processors for expanding the number of input channels using Programmable Real-time Unit (PRU-ICSS). ADCs are configured for simultaneous sampling of the same channels across all ADCs. The design highlights the capability of PRU-ICSS to handle 1536ksps (each sample = 16 bits) data rate by sampling 640 samples per line cycle. For 50Hz cycle, this corresponds to 32ksps per channel across 6 ADCs simultaneously (640 samples/cycle*50Hz*6 ADCs*8 Ch = 1536ksps). Also, the second PRU is used to post process the data to achieve coherent sampling.
Features
- Flexible interface using PRU-ICSS (Sitara Processor) for communicating with multiple SAR ADCs
- AC voltage and current measurement accuracy:
- AC Voltage: <±0.2% for 2.5V to 120V
- AC Current: <±0.2% for 2.5A to 70A
- Simultaneous sampling across six ADCs (16-bit, 500ksps/ADC)
- PRU-ICSS Interface:
- Programmable real-time unitiIndustrial communication subsystem (PRU-ICSS) offers flexible data capture for channel expansion
- Firmware-based approach allows for reuse across different Sitara processors
- Coherent sampling is achieved by computing line cycle in software and by adjusting CS signal
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TI Devices (14)
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| Sample & Buy |
Design Kits & Evaluation Modules |
| ADS8688 |
16-Bit 500kSPS 8-Channel Single-Supply SAR ADC With Bipolar Input Ranges |
Analog-to-digital converters (ADCs) |
Sample & Buy |
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| AM3356 |
Sitara processor: Arm Cortex-A8, PRU-ICSS, CAN |
Sitara processors |
Sample & Buy |
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| AM3357 |
Sitara processor: Arm Cortex-A8, EtherCAT, PRU-ICSS, CAN |
Sitara processors |
Sample & Buy |
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| AM3358 |
Sitara processor: Arm Cortex-A8, 3D graphics, PRU-ICSS, CAN |
Sitara processors |
Sample & Buy |
View Design Kits & Evaluation Modules |
| AM3359 |
Sitara processor: Arm Cortex-A8, EtherCAT, 3D, PRU-ICSS, CAN |
Sitara processors |
Sample & Buy |
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| CDCLVC1106 |
Low Jitter, 1:6 LVCMOS Fan-out Clock Buffer |
Clocks & timing |
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| LP2992 |
250-mA, 16-V, low-dropout voltage regulator with enable |
Power management |
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| OPA4197 |
Quad, 36-V, Precision, Rail-to-Rail Input Output, Low Offset Voltage Op Amp
|
Operational amplifiers (op amps) |
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| SN74LV1T04 |
Single Power Supply INVERTER Gate logic level shifter |
Voltage level translators |
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| SN74LVC1G17 |
Single Schmitt-Trigger Buffer |
Buffer/driver |
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| TPS22914 |
5.5-V, 2-A, 37-mΩ load switch |
Power switches |
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| TPS65131 |
Split-Rail Converter with Dual, Positive and Negative Outputs (750mA typ) |
Power management |
Sample & Buy |
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| TPS7A39 |
150-mA, 33-V, low-noise, high-PSRR, dual-channel positive & negative low-dropout voltage regulator |
Power management |
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| TPS7A65-Q1 |
Automotive 300-mA, off-battery (40-V), low-IQ, low-dropout voltage regulator |
Power management |
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Technical documentation
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Application notes (1)
| Title | Type | Size (KB) | Date |
| | PDF | 1042 |
17 Apr 2018
|
User guides (1)
| Title | Type | Size (KB) | Date |
| | PDF | 1929 |
03 Jan 2019
|
Design files (6)
| | ZIP | 287 |
06 Feb 2019
|
| | ZIP | 7628 |
20 Dec 2017
|
| | ZIP | 5446 |
20 Dec 2017
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| | ZIP | 4674 |
20 Dec 2017
|
| | ZIP | 733 |
20 Dec 2017
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| | ZIP | 1659 |
20 Dec 2017
|
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