Flexible Interface (PRU-ICSS) Reference Design for Simultaneous, Coherent DAQ Using Multiple ADCs
TIDA-01555
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This product has been released to the market and is available for purchase. For some products, newer alternatives may be available.
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Key Document
- Flexible Interface (PRU-ICSS) Reference Design for Simultaneous, Coherent DAQ (Rev. A)
(PDF 1929 KB)
03 Jan 2019
Description
This reference design showcases an interface implementation for connecting multiple high voltage bipolar input, 8-channel, mux-input SAR ADCs (6) with the Sitara Arm processors for expanding the number of input channels using Programmable Real-time Unit (PRU-ICSS). ADCs are configured for simultaneous sampling of the same channels across all ADCs. The design highlights the capability of PRU-ICSS to handle 1536ksps (each sample = 16 bits) data rate by sampling 640 samples per line cycle. For 50Hz cycle, this corresponds to 32ksps per channel across 6 ADCs simultaneously (640 samples/cycle*50Hz*6 ADCs*8 Ch = 1536ksps). Also, the second PRU is used to post process the data to achieve coherent sampling.
Features
- Flexible interface using PRU-ICSS (Sitara Processor) for communicating with multiple SAR ADCs
- AC voltage and current measurement accuracy:
- AC Voltage: <±0.2% for 2.5V to 120V
- AC Current: <±0.2% for 2.5A to 70A
- Simultaneous sampling across six ADCs (16-bit, 500ksps/ADC)
- PRU-ICSS Interface:
- Programmable real-time unitiIndustrial communication subsystem (PRU-ICSS) offers flexible data capture for channel expansion
- Firmware-based approach allows for reuse across different Sitara processors
- Coherent sampling is achieved by computing line cycle in software and by adjusting CS signal
See the Important Notice and Disclaimer covering reference designs and other TI resources.
