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Product details

Parameters

Function Single-ended Additive RMS jitter (Typ) (fs) 70 Output frequency (Max) (MHz) 250 Number of outputs 6 VCC out (V) 2.5, 3.3 VCC core (V) 2.5, 3.3 Output skew (ps) 50 Features 1:6 fanout, Output enable control Operating temperature range (C) -40 to 85 Rating Catalog Output type LVCMOS Input type LVCMOS open-in-new Find other Clock buffers

Package | Pins | Size

TSSOP (PW) 14 32 mm² 5 x 6.4 open-in-new Find other Clock buffers

Features

  • High-Performance 1:2, 1:3, 1:4, 1:6, 1:8, 1:10, 1:12 LVCMOS Clock Buffer Family
  • Very Low Pin-to-Pin Skew < 50 ps
  • Very Low Additive Jitter < 100 fs
  • Supply Voltage: 3.3 V or 2.5 V
  • fmax = 250 MHz for 3.3 V
    fmax = 180 MHz for 2.5 V
  • Operating Temperature Range: –40°C to 85°C
  • Available in 8-, 14-, 16-, 20-, 24-Pin TSSOP Package (All Pin-Compatible)

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Description

The CDCLVC11xx is a modular, high-performance, low-skew, general-purpose clock buffer family from Texas Instruments.

The entire family is designed with a modular approach in mind. It is intended to round up TI’s series of LVCMOS clock generators.

Seven different fan-out variations, 1:2 to 1:12, are available. All of the devices are pin-compatible to each other for easy handling.

All family members share the same high performing characteristics such as low additive jitter, low skew, and wide operating temperature range.

The CDCLVC11xx supports an asynchronous output enable control (1G) which switches the outputs into a low state when 1G is low.

The CDCLVC11xx family operates in a 2.5-V and
3.3-V environment and are characterized for operation from –40°C to 85°C.

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Technical documentation

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Type Title Date
* Datasheet CDCLVC11xx 3.3-V and 2.5-V LVCMOS High-Performance Clock Buffer Family datasheet (Rev. B) Feb. 24, 2017
Selection guides Clock & Timing Solutions (Rev. C) Jan. 19, 2017
Application notes How to Apply 1.8-V Signals to 3.3-V CDCLVC11xx Fanout Clock Buffer Nov. 30, 2010

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$149.00
Description
The CDCLVC1112 is a high-performance, low additive phase noise LVCMOS clock buffer. It has one LVCMOS input and twelve LVCMOS outputs. It has also an enable pin. This evaluation module (EVM) is designed to demonstrate the electrical performance of the CDCLVC1112. However, this EVM can also be used (...)
Features
  • Easy-to-use evaluation board to fan out low phase noise LVCMOS clock signals
  • Easy device setup
  • Enable pin configurable though jumper and SMA
  • Board powered at 3.3V
EVALUATION BOARDS Download
document-generic User guide
$999.00
Description

This board supports: TAS2555YZEVMTAS2557EVM and TAS2559EVM.

The Smart Amplifier Speaker Characterization Board, when used in conjunction with a supported TI Smart Amplifier and PurePath Console software, provides users the ability to measure speaker excursion, temperature and other parameters for (...)

Features
  • Easily and quickly characterize speakers
  • Quick connection to TI Smart Amplifier EVMs
  • Microphone included for SPL measurements
  • Laser input for speaker excursion measurements

Design tools & simulation

SIMULATION MODELS Download
SLLM088B.ZIP (263 KB) - IBIS Model

Reference designs

REFERENCE DESIGNS Download
Flexible Interface (PRU-ICSS) Reference Design for Simultaneous, Coherent DAQ Using Multiple ADCs
TIDA-01555 — This reference design showcases an interface implementation for connecting multiple high voltage bipolar input, 8-channel, mux-input SAR ADCs (6) with the Sitara Arm processors for expanding the number of input channels using Programmable Real-time Unit (PRU-ICSS). ADCs are configured for (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Low-Voltage, Low-Noise Power-Supply Reference Design for Ultrasound Front End
TIDA-01466 — This reference design is a power supply optimized specifically for providing power to eight 16-channel receive AFE ICs for ultrasound imaging systems. This design reduces part count while maximizing efficiency by using single-chip DC-DC converter + LDO combo regulators to set the LDO input just (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
TSSOP (PW) 14 View options

Ordering & quality

Support & training

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