SPI Master with Signal Path Delay Compensation Reference Design


Design files


The Programmable Real-time Unit within the Industrial Communication Subsystem (PRU-ICSS) enables you to support real-time critical applications without using FPGAs, CPLDs or ASICs.
This reference design describes the implementation of the SPI master protocol with signal path delay compensation on PRU-ICSS. It supports the 32-bit communication protocol of ADS8688 with a SPI clock frequency of up to 16.7 MHz.

  • SPI master protocol with adjustable signal path delay compensation (not requiring external hardware for signal path delay compensation)
  • Up to 16.7-MHz SPI clock
  • Supports ADS8688 SPI-communication protocol
  • Automatic measurement of signal path delay for known secondary response
  • This PRU-ICSS firmware has been validated with TIDA-00164 (ADS8688 and ISO7141CC) and contains firmware source code, implementation description and getting started instructions.
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A fully assembled board has been developed for testing and performance validation only, and is not available for sale.

Design files & products

Design files

Download ready-to-use system files to speed your design process.

TIDUA38A.PDF (1141 K)

Reference design overview and verified performance test data

TIDRF78.PDF (248 K)

Detailed schematic diagram for design layout and components

TIDRF79.PDF (124 K)

Complete listing of design components, reference designators, and manufacturers/part numbers

TIDRF80.ZIP (447 K)

Detailed overview of design layout for component placement

TIDRF82.ZIP (384 K)

Files used for 3D models or 2D drawings of IC components

TIDCAG2.ZIP (5563 K)

Design file that contains information on physical board layer of design PCB

TIDRF81.ZIP (447 K)

PCB layer plot file used for generating PCB design layout


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Technical documentation

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Type Title Date
* Design guide SPI Master With Signal Path Delay Compensation on PRU-ICSS Design Guide (Rev. A) Jul. 13, 2015

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