Product details
Parameters
Package | Pins | Size
Features
- Available in the Texas Instruments NanoStar™ Package
- Low Static-Power Consumption
(ICC = 0.9 µA Max) - Low Dynamic-Power Consumption
(Cpd = 4.3 pF Typ at 3.3 V) - Low Input Capacitance (Ci = 1.5 pF Typ)
- Low Noise – Overshoot and Undershoot
<10% of VCC - Ioff Supports Partial-Power-Down Mode Operation
- Schmitt-Trigger Action Allows Slow Input Transition and
Better Switching Noise Immunity at the Input
(Vhys = 250 mV Typ at 3.3 V) - Wide Operating VCC Range of 0.8 V to 3.6 V
- Optimized for 3.3-V Operation
- 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
- tpd = 5.9 ns Max at 3.3 V
- Suitable for Point-to-Point Applications
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model
(A114-B, Class II) - 1000-V Charged-Device Model (C101)
- 2000-V Human-Body Model
NanoStar is a trademark of Texas Instruments.
Description
The AUP family is TIs premier solution to the industrys low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).
This dual 2-input positive-AND gate performs the Boolean function Y = A B or Y = A\ + B\ in positive logic.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | SN74AUP2G08 Low-Power Dual 2-Input Positive-AND Gate datasheet (Rev. C) | Dec. 30, 2009 |
Technical article | How to keep your motor running safely | Jun. 04, 2020 | |
Selection guide | Little Logic Guide 2018 (Rev. G) | Jul. 06, 2018 | |
Selection guide | Logic Guide (Rev. AB) | Jun. 12, 2017 | |
Application note | How to Select Little Logic (Rev. A) | Jul. 26, 2016 | |
Application note | Understanding Schmitt Triggers | Sep. 21, 2011 | |
Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | Jul. 08, 2004 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
Features
- Board design allows for versatility in evaluation
- Supports a wide-range of logic devices
Design tools & simulation
Reference designs
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
DSBGA (YFP) | 8 | View options |
DSBGA (YZP) | 8 | View options |
UQFN (RSE) | 8 | View options |
VSSOP (DCU) | 8 | View options |
X2SON (DQE) | 8 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Support & training
TI E2E™ forums with technical support from TI engineers
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If you have questions about quality, packaging or ordering TI products, see TI support.