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This device is designed to have an ultralow quiescent current and be stable with a 4.7-µF capacitor. This combination provides high performance at a reasonable cost.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 230 mV at an output current of 250 mA for the TPS76650) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 35 µA over the full range of output current, 0 mA to 250 mA). These two key specifications yield a significant improvement in operating life for battery-powered systems. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to less than 1 µA (typ).
Power good (PG) is an active high output that can be used to implement a power-on reset or a low-battery indicator.
The TPS766xx is offered in 1.5 V, 1.8 V, 2.5 V, 2.7 V, 2.8 V, 3.0 V, 3.3 V and 5.0 V fixed voltage versions and in an adjustable version (programmable over the range of 1.25 V to 5.5 V). Output voltage tolerance is specified as a maximum of 3% over line, load, and temperature ranges. The TPS766xx family is available in an 8-pin SOIC package.
| Type | Title | Date | |
|---|---|---|---|
| * | Data sheet | Ultra Low Quiescent Current 250-mA Low-Dropout Voltage Regulators datasheet (Rev. C) | 08 Jan 2009 |
| Application note | LDO Noise Demystified (Rev. B) | 18 Aug 2020 | |
| Application note | LDO PSRR Measurement Simplified (Rev. A) | 09 Aug 2017 | |
| Analog Design Journal | Discrete design of a low-cost isolated 3.3- to 5-V DC/DC converter | 06 May 2010 |
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| Package | Pins | Download |
|---|---|---|
| SOIC (D) | 8 | View options |
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