The K2E requires the use of AVS SmartReflex control for the CVDD core voltage. This design provides method of generating the proper voltage using software and the PMBus interface of the TPS544C25. The circuit can be implemented on the XEVMK2EX.
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
Download ready-to-use system files to speed your design process.
Reference design overview and verified performance test data
Detailed schematic diagram for design layout and components
Complete listing of design components, reference designators, and manufacturers/part numbers
Design file that contains information on physical board layer of design PCB
PCB layer plot file used for generating PCB design layout
Includes TI products in the design and potential alternatives.
| Type | Title | Date | |
|---|---|---|---|
| * | Design guide | Generating AVS SmartReflex Core Voltage for K2E SOC Design Guide | Aug. 18, 2015 |
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