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Product details

Parameters

Arm MHz (Max.) 1250, 1400 DRAM DDR3, DDR3L Arm CPU 2 Arm Cortex-A15 Ethernet MAC 8-Port 1Gb Switch USB 2 SPI 3 I2C 3 Operating temperature range (C) 0 to 85, -40 to 100 Serial I/O Hyperlink, I2C, SPI, TSIP, UART, USB UART 2 open-in-new Find other Other Sitara processors

Features

  • ARM® Cortex®-A15 MPCore™ CorePac
    • Up to Four ARM Cortex-A15 Processor Cores at
      up to 1.4-GHz
    • 4MB L2 Cache Memory Shared by all Cortex-
      A15 Processor Cores
    • Full Implementation of ARMv7-A Architecture
      Instruction Set
    • 32KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE)
      Master Port, Connected to MSMC (Multicore
      Shared Memory Controller) for Low Latency
      Access to SRAM and DDR3
  • Multicore Shared Memory Controller (MSMC)
    • 2 MB SRAM Memory for ARM CorePac
    • Memory Protection Unit for Both SRAM and
      DDR3_EMIF
  • Multicore Navigator
    • 8k Multi-Purpose Hardware Queues with Queue
      Manager
    • One Packet-Based DMA Engine for Zero-
      Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP,
        PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1 Gbps Wire Speed Throughput at 1.5
        MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP and WiMAX Air
        Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM,
        HMAC, CMAC, GMAC, AES, DES, 3DES,
        Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit
        Hash), MD5
      • Up to 6.4 Gbps IPSec and 3 Gbps Air
        Ciphering
    • Ethernet Subsystem
      • Eight SGMII Ports with Wire Rate Switching
      • IEEE1588 v2 (with Annex D/E/F) Support
      • 8 Gbps Total Ingress/Egress Ethernet BW
        from Core
      • Audio/Video Bridging (802.1Qav/D6.0)
      • QOS Capability
      • DSCP Priority Mapping
  • Peripherals
    • Two PCIe Gen2 Controllers with Support for
      • Two Lanes per Controller
      • Supports Up to 5 GBaud
    • One HyperLink
      • Supports Connections to Other KeyStone Architecture
        Devices Providing Resource
        Scalability
      • Supports Up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem
      • Two SGMII/XFI Ports with Wire Rate
        Switching and MACSEC Support
      • IEEE1588 v2 (with Annex D/E/F) Support
    • One 72-Bit DDR3/DDR3L Interface with Speeds Up
      to 1600 MTPS in DDR3 Mode
    • EMIF16 Interface
    • Two USB 2.0/3.0 Controllers
    • USIM Interface
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • One TSIP
      • Support 1024 DS0s
      • Support 2 Lanes at 32.768/16.3848.192
        Mbps Per Lane
  • System Resources
    • Three On-Chip PLLs
    • SmartReflex Automatic Voltage Scaling
    • Semaphore Module
    • Twelve 64-Bit Timers
    • Five Enhanced Direct Memory Access (EDMA)
      Modules
  • Commercial Case Temperature:
    • 0°C to 85°C
  • Extended Case Temperature:
    • –40°C to 100°C
open-in-new Find other Other Sitara processors

Description

The AM5K2E0x is a high performance device based on TI’s KeyStone II Multicore SoC Architecture, incorporating the most performance-optimized Cortex-A15 processor dual-core or quad-core CorePac that can run at a core speed of up to 1.4 GHz. TI’s AM5K2E0x device enables a high performance, power-efficient and easy to use platform for developers of a broad range of applications such as enterprise grade networking end equipment, data center networking, avionics and defense, medical imaging, test and automation.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (for example, ARM CorePac (Cortex-A15 Processor Quad Core CorePac), network processing, and uses a queue-based communication system that allows the device resources to operate efficiently and seamlessly. This unique device architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

The AM5K2E0x KeyStone II device integrates a large amount of on-chip memory. The Cortex-A15 processor cores each have 32KB of L1Data and 32KB of L1 Instruction cache. The up to four Cortex A15 cores in the ARM CorePac share a 4MB L2 Cache. The device also integrates 2MB of Multicore Shared Memory (MSMC) that can be used as a shared L3 SRAM. All L2 and MSMC memories incorporate error detection and error correction. For fast access to external memory, this device includes a 64-bit DDR-3 (72-bit with ECC support) external memory interface (EMIF) running at 1600 MTPS.

The device enables developers to use a variety of development and debugging tools that include GNU GCC, GDB, Open source Linux, Eclipse based debugging environment enabling kernel and user space debugging using a variety of Eclipse plug-ins including TI's industry leading IDE Code Composer Studio.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 57
Type Title Date
* Datasheet AM5K2E04/02 Multicore ARM KeyStone II System-on-Chip (SoC) datasheet (Rev. D) Mar. 11, 2015
* Errata AM5K2E04/02 KeyStone SoC Silicon Errata (Silicon Rev 1.0) (Rev. B) Aug. 20, 2015
Technical articles How to affordably add EtherNet/IP, EtherCAT and PROFINET to an autonomous factory Aug. 24, 2020
Technical articles Designing smarter remote terminal units for microgrids Oct. 02, 2019
Application notes Using Arm ROM Bootloader on Keystone II Devices Jun. 04, 2019
Technical articles Security versus functional safety: a view from the Processor Software Development Kit May 31, 2019
Application notes Keystone Multicore Device Family Schematic Checklist May 17, 2019
Application notes KeyStone II DDR3 interface bring-up Mar. 07, 2019
Technical articles Simplified software development through the Processor SDK and tools Oct. 02, 2018
User guides How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS Sep. 24, 2018
Application notes DDR3 Design Requirements for KeyStone Devices (Rev. C) Jan. 23, 2018
User guides KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) (Rev. A) Aug. 21, 2017
Application notes Thermal Design Guide for DSP and Arm Application Processors (Rev. B) Aug. 14, 2017
User guides Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I) Jul. 26, 2017
Application notes Power Consumption Summary for K2E System-on-Chip (SoC) Device Family Jun. 14, 2017
Selection guides TI Components for Aerospace and Defense Guide (Rev. E) Mar. 22, 2017
Application notes Clocking Spreadsheet for K2E Device Family Jan. 26, 2017
User guides Serializer/Deserializer (SerDes) for KeyStone II Devices User Guide (Rev. A) Jul. 27, 2016
Application notes Power Management of KS2 Device (Rev. C) Jul. 15, 2016
Application notes Throughput Performance Guide for KeyStone II Devices (Rev. B) Dec. 22, 2015
Application notes Keystone II DDR3 Debug Guide Oct. 16, 2015
User guides Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B) May 06, 2015
User guides Gigabit Ethernet (GbE) Switch SS for K2E & K2L Devices User's Guide (Rev. A) Apr. 28, 2015
User guides Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H) Apr. 09, 2015
User guides DDR3 Memory Controller for KeyStone II Devices User's Guide (Rev. C) Mar. 27, 2015
White papers Save power and costs with TI's K2E on-chip networking features Mar. 25, 2015
Application notes Keystone II DDR3 Initialization Jan. 26, 2015
User guides Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C) Sep. 04, 2014
White papers KeyStone™-II-based processors: 10G Ethernet as an optical interface Aug. 25, 2014
User guides Packet Accelerator 2 (PA2) for K2E and K2L Devices User's Guide Aug. 19, 2014
User guides Security Accelerator 2 (SA2) for K2E and K2L Devices User's Guide Aug. 19, 2014
White papers Differentiating AM5K2E02 and AM5K2E04 SoCs from Alternate ARM® Cortex®-A15 Devic Aug. 14, 2014
User guides Network Coprocessor (NETCP) for K2E and K2L Devices User's Guide Aug. 13, 2014
Application notes Hardware Design Guide for KeyStone II Devices Mar. 24, 2014
User guides PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D) Sep. 30, 2013
User guides Debug and Trace for KeyStone II Devices User's Guide Jul. 26, 2013
User guides ARM Bootloader User Guide for KeyStone II Devices Jul. 21, 2013
User guides Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A) Jun. 28, 2013
User guides HyperLink for KeyStone Devices User's Guide (Rev. C) May 28, 2013
User guides Multicore Shared Memory Controller (MSMC) User Guide for KeyStone II Devices Nov. 12, 2012
More literature Industrial Imaging: Applications of the K2H and K2E platforms Nov. 09, 2012
More literature Video Infrastructure - Applications of the K2E, K2H platforms Nov. 09, 2012
More literature OpenMP Programming for TMS320C66x Multicore DSPs (Rev. A) Nov. 05, 2012
User guides ARM CorePac User Guide for KeyStone II Devices Oct. 31, 2012
Application notes Multicore Programming Guide (Rev. B) Aug. 29, 2012
User guides Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A) Mar. 30, 2012
User guides Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A) Mar. 27, 2012
User guides 64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A) Mar. 22, 2012
Application notes PCIe Use Cases for KeyStone Devices Dec. 13, 2011
User guides Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide Sep. 02, 2011
User guides External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A) May 24, 2011
User guides C66x DSP Cache User's Guide Nov. 09, 2010
Application notes Clocking Design Guide for KeyStone Devices Nov. 09, 2010
User guides General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide Nov. 09, 2010
Application notes Optimizing Loops on the C66x DSP Nov. 09, 2010
User guides Telecom Serial Interface Port (TSIP) for KeyStone Devices User's Guide Nov. 09, 2010
User guides Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG Nov. 09, 2010

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
eInfochips System on Modules and EVMs
Provided by eInfochips
Description

eInfochips is a product engineering and design services company with over 20 years of experience, 500+ product developments, and over 40M deployments in 140 countries, across the world. The company has delivered turnkey technology solutions for many Fortune 500 companies, across multiple verticals (...)

DEVELOPMENT KITS Download
document-generic User guide
997
Description

The EVMK2EX is a full-featured development tool for 66AK2Exx and AM5K2Exx KeyStone II based SoCs. Get started developing general purpose embedded computing systems for industrial, mission critical, and networking applications today with this double-wide AMC form-factor evaluation board featuring a (...)

Features

EVMK2EX

  • Example Applications- Avionics, embedded industrial controls, embedded networking, industrial routing & switching, and general purpose embedded computing systems
  • Board size- Double Wide PICMG ® AMC form factor (7.11” x 2.89”)
  • DDR memory- 4GB ECC DDR3 1600 SO-DIMM
  • Development environment- DCode (...)

Software development

SOFTWARE DEVELOPMENT KITS (SDK) Download
Processor SDK for 66AK2Ex Processors - Linux and TI-RTOS support
PROCESSOR-SDK-K2E  

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

Features

 

Linux features

  • Open Linux support
  • Linux kernel and Bootloaders
  • File system
  • GUI-based application launcher
  • Example applications, including:
    • ARM benchmarks: Dhrystone, Linpack, Whetstone
    • Cryptography: AES, 3DES, MD5, SHA
  • Host tools including flash utility
  • Code Composer Studio™ IDE for Linux development
  • (...)
DEBUG PROBES Download
XDS200 USB Debug Probe
TMDSEMU200-U The Spectrum Digital XDS200 is the first model of the XDS200 family of debug probes (emulators) for TI processors. The XDS200 family features a balance of low cost with good performance between the super low cost XDS110 and the high performance XDS560v2, while supporting a wide variety of standards (...)
295
Features

The XDS200 is the mid-range family of JTAG debug probes (emulators) for TI processors. Designed to deliver good performance and the most common features that place it between the low cost XDS110 and the high performance XDS560v2, the XDS200 is the balanced solution to debug TI microcontrollers (...)

DEBUG PROBES Download
XDS560v2 System Trace USB Debug Probe
TMDSEMU560V2STM-U The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

995
Features

XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

DEBUG PROBES Download
XDS560v2 System Trace USB & Ethernet Debug Probe
TMDSEMU560V2STM-UE The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

1495
Features
  • XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

IDES, CONFIGURATION, COMPILERS & DEBUGGERS Download
Code Composer Studio (CCS) Integrated Development Environment (IDE) for Multicore Processors
CCSTUDIO-KEYSTONE

Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor (...)

OPERATING SYSTEMS (OS) Download
HCC Embedded TI-RTOS software
Provided by HCC-Embedded — For more than a decade HCC has focused on developing re-usable embedded software components for Flash, file systems and communications. Many of the leading RTOS vendors in the industry re-sell HCC software under their own brand, giving engineers access to excellent middleware regardless of the RTOS (...)

Design tools & simulation

SIMULATION MODELS Download
SPRM621.ZIP (2180 KB) - IBIS Model
SIMULATION MODELS Download
SPRM622.ZIP (5 KB) - Thermal Model
SIMULATION MODELS Download
SPRM623.ZIP (28 KB) - BSDL Model
SIMULATION MODELS Download
SPRM653A.ZIP (142 KB) - Power Model
SIMULATION MODELS Download
SPRM743.ZIP (265889 KB) - IBIS-AMI Model
CALCULATION TOOLS Download
Clock Tree Tool for Sitara, Automotive, Vision Analytics, & Digital Signal Processors
CLOCKTREETOOL The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:
  • Visualize the device clock tree
  • Interact with clock tree elements (...)
document-generic User guide
SCHEMATICS Download
SPRR197.ZIP (99 KB)

Reference designs

REFERENCE DESIGNS Download
Generating AVS SmartReflex Core Voltage for K2E Using TPS544C25 and PMBus Reference Design
TIDEP0042 The K2E requires the use of AVS SmartReflex control for the CVDD core voltage. This design provides method of generating the proper voltage using software and the PMBus interface of the TPS544C25. The circuit can be implemented on the XEVMK2EX.
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Generating AVS SmartReflex core voltage, PMBus for K2E reference design
TIDEP0041 The K2E requires the use of AVS SmartReflex control for the CVDD core voltage. This design provides method of generating the proper voltage without the need for any software. The circuit is currently implemented on the XEVMK2EX.
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Power Sequencing for K2E Using UCD9090 with PMBus
TIDEP0031 The K2E devices require power supplies to be sequenced in a proper order. This design demonstrates power sequencing for the 66AK2Ex and AM5K2Ex families of KeyStone II ARM+DSP and ARM-only multicore processors by use of the UCD9090. The UCD9090 is a 10-rail PMBus/I2C addressable power-supply (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
K2E Clock Generation Reference Design
TIDEP0026 A single clock source should not be used to drive multiple clock inputs for a high-performance processor device, such as multicore ARM Cortex-A15 based 66AK2Ex and AM5K2Ex processors, since excessive loading, reflections, and noise will negatively impact performance. These can be avoided through the (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
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