AM5K2E02

• ARM^® Cortex^®-A15 MPCore™ CorePac
  • Up to Four ARM Cortex-A15 Processor Cores at
    up to 1.4-GHz
  • 4MB L2 Cache Memory Shared by all Cortex-
    A15 Processor Cores
  • Full Implementation of ARMv7-A Architecture
    Instruction Set
  • 32KB L1 Instruction and Data Caches per Core
  • AMBA 4.0 AXI Coherency Extension (ACE)
    Master Port, Connected to MSMC (Multicore
    Shared Memory Controller) for Low Latency
    Access to SRAM and DDR3
• Multicore Shared Memory Controller (MSMC)
  • 2 MB SRAM Memory for ARM CorePac
  • Memory Protection Unit for Both SRAM and
    DDR3_EMIF
• Multicore Navigator
  • 8k Multi-Purpose Hardware Queues with Queue
    Manager
  • One Packet-Based DMA Engine for Zero-
    Overhead Transfers
• Network Coprocessor
  • Packet Accelerator Enables Support for
    • Transport Plane IPsec, GTP-U, SCTP,
      PDCP
    • L2 User Plane PDCP (RoHC, Air Ciphering)
    • 1 Gbps Wire Speed Throughput at 1.5
      MPackets Per Second
  • Security Accelerator Engine Enables Support for
    • IPSec, SRTP, 3GPP and WiMAX Air
      Interface, and SSL/TLS Security
    • ECB, CBC, CTR, F8, A5/3, CCM, GCM,
      HMAC, CMAC, GMAC, AES, DES, 3DES,
      Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit
      Hash), MD5
    • Up to 6.4 Gbps IPSec and 3 Gbps Air
      Ciphering
  • Ethernet Subsystem
    • Eight SGMII Ports with Wire Rate Switching
    • IEEE1588 v2 (with Annex D/E/F) Support
    • 8 Gbps Total Ingress/Egress Ethernet BW
      from Core
    • Audio/Video Bridging (802.1Qav/D6.0)
    • QOS Capability
    • DSCP Priority Mapping
• Peripherals
  • Two PCIe Gen2 Controllers with Support for
    • Two Lanes per Controller
    • Supports Up to 5 GBaud
  • One HyperLink
    • Supports Connections to Other KeyStone Architecture
      Devices Providing Resource
      Scalability
    • Supports Up to 50 GBaud
  • 10-Gigabit Ethernet (10-GbE) Switch Subsystem
    • Two SGMII/XFI Ports with Wire Rate
      Switching and MACSEC Support
    • IEEE1588 v2 (with Annex D/E/F) Support
  • One 72-Bit DDR3/DDR3L Interface with Speeds Up
    to 1600 MTPS in DDR3 Mode
  • EMIF16 Interface
  • Two USB 2.0/3.0 Controllers
  • USIM Interface
  • Two UART Interfaces
  • Three I²C Interfaces
  • 32 GPIO Pins
  • Three SPI Interfaces
  • One TSIP
    • Support 1024 DS0s
    • Support 2 Lanes at 32.768/16.3848.192
      Mbps Per Lane
• System Resources
  • Three On-Chip PLLs
  • SmartReflex Automatic Voltage Scaling
  • Semaphore Module
  • Twelve 64-Bit Timers
  • Five Enhanced Direct Memory Access (EDMA)
    Modules
• Commercial Case Temperature:
  • 0°C to 85°C
• Extended Case Temperature:
  • –40°C to 100°C

The AM5K2E0x is a high performance device based on TI’s KeyStone II Multicore SoC Architecture, incorporating the most performance-optimized Cortex-A15 processor dual-core or quad-core CorePac that can run at a core speed of up to 1.4 GHz. TI’s AM5K2E0x device enables a high performance, power-efficient and easy to use platform for developers of a broad range of applications such as enterprise grade networking end equipment, data center networking, avionics and defense, medical imaging, test and automation.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (for example, ARM CorePac (Cortex-A15 Processor Quad Core CorePac), network processing, and uses a queue-based communication system that allows the device resources to operate efficiently and seamlessly. This unique device architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

The AM5K2E0x KeyStone II device integrates a large amount of on-chip memory. The Cortex-A15 processor cores each have 32KB of L1Data and 32KB of L1 Instruction cache. The up to four Cortex A15 cores in the ARM CorePac share a 4MB L2 Cache. The device also integrates 2MB of Multicore Shared Memory (MSMC) that can be used as a shared L3 SRAM. All L2 and MSMC memories incorporate error detection and error correction. For fast access to external memory, this device includes a 64-bit DDR-3 (72-bit with ECC support) external memory interface (EMIF) running at 1600 MTPS.

The device enables developers to use a variety of development and debugging tools that include GNU GCC, GDB, Open source Linux, Eclipse based debugging environment enabling kernel and user space debugging using a variety of Eclipse plug-ins including TI's industry leading IDE Code Composer Studio.