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AM5K2E02

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Sitara processor: dual-Arm Cortex-A15

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Data sheet
Errata
Sitara processor: dual-Arm Cortex-A15

AM5K2E02

ACTIVE
Data sheet Order now

Product details

Arm CPU 2 Arm Cortex-A15 Arm MHz (Max.) 1250, 1400 Co-processor(s) Network co-processor CPU 32-bit Protocols Ethernet Ethernet MAC 8-Port 1Gb Switch PCIe 4 PCIe Gen 2 Hardware accelerators Packet Accelerator, Security Accelerator Features Networking Operating system Linux, RTOS Rating Catalog Operating temperature range (C) 0 to 85, -40 to 100
Arm CPU 2 Arm Cortex-A15 Arm MHz (Max.) 1250, 1400 Co-processor(s) Network co-processor CPU 32-bit Protocols Ethernet Ethernet MAC 8-Port 1Gb Switch PCIe 4 PCIe Gen 2 Hardware accelerators Packet Accelerator, Security Accelerator Features Networking Operating system Linux, RTOS Rating Catalog Operating temperature range (C) 0 to 85, -40 to 100
open-in-new Find other Arm-based processors
  • ARM® Cortex®-A15 MPCore™ CorePac
    • Up to Four ARM Cortex-A15 Processor Cores at
      up to 1.4-GHz
    • 4MB L2 Cache Memory Shared by all Cortex-
      A15 Processor Cores
    • Full Implementation of ARMv7-A Architecture
      Instruction Set
    • 32KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE)
      Master Port, Connected to MSMC (Multicore
      Shared Memory Controller) for Low Latency
      Access to SRAM and DDR3
  • Multicore Shared Memory Controller (MSMC)
    • 2 MB SRAM Memory for ARM CorePac
    • Memory Protection Unit for Both SRAM and
      DDR3_EMIF
  • Multicore Navigator
    • 8k Multi-Purpose Hardware Queues with Queue
      Manager
    • One Packet-Based DMA Engine for Zero-
      Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP,
        PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1 Gbps Wire Speed Throughput at 1.5
        MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP and WiMAX Air
        Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM,
        HMAC, CMAC, GMAC, AES, DES, 3DES,
        Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit
        Hash), MD5
      • Up to 6.4 Gbps IPSec and 3 Gbps Air
        Ciphering
    • Ethernet Subsystem
      • Eight SGMII Ports with Wire Rate Switching
      • IEEE1588 v2 (with Annex D/E/F) Support
      • 8 Gbps Total Ingress/Egress Ethernet BW
        from Core
      • Audio/Video Bridging (802.1Qav/D6.0)
      • QOS Capability
      • DSCP Priority Mapping
  • Peripherals
    • Two PCIe Gen2 Controllers with Support for
      • Two Lanes per Controller
      • Supports Up to 5 GBaud
    • One HyperLink
      • Supports Connections to Other KeyStone Architecture
        Devices Providing Resource
        Scalability
      • Supports Up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem
      • Two SGMII/XFI Ports with Wire Rate
        Switching and MACSEC Support
      • IEEE1588 v2 (with Annex D/E/F) Support
    • One 72-Bit DDR3/DDR3L Interface with Speeds Up
      to 1600 MTPS in DDR3 Mode
    • EMIF16 Interface
    • Two USB 2.0/3.0 Controllers
    • USIM Interface
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • One TSIP
      • Support 1024 DS0s
      • Support 2 Lanes at 32.768/16.3848.192
        Mbps Per Lane
  • System Resources
    • Three On-Chip PLLs
    • SmartReflex Automatic Voltage Scaling
    • Semaphore Module
    • Twelve 64-Bit Timers
    • Five Enhanced Direct Memory Access (EDMA)
      Modules
  • Commercial Case Temperature:
    • 0°C to 85°C
  • Extended Case Temperature:
    • –40°C to 100°C
  • ARM® Cortex®-A15 MPCore™ CorePac
    • Up to Four ARM Cortex-A15 Processor Cores at
      up to 1.4-GHz
    • 4MB L2 Cache Memory Shared by all Cortex-
      A15 Processor Cores
    • Full Implementation of ARMv7-A Architecture
      Instruction Set
    • 32KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE)
      Master Port, Connected to MSMC (Multicore
      Shared Memory Controller) for Low Latency
      Access to SRAM and DDR3
  • Multicore Shared Memory Controller (MSMC)
    • 2 MB SRAM Memory for ARM CorePac
    • Memory Protection Unit for Both SRAM and
      DDR3_EMIF
  • Multicore Navigator
    • 8k Multi-Purpose Hardware Queues with Queue
      Manager
    • One Packet-Based DMA Engine for Zero-
      Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP,
        PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1 Gbps Wire Speed Throughput at 1.5
        MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP and WiMAX Air
        Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM,
        HMAC, CMAC, GMAC, AES, DES, 3DES,
        Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit
        Hash), MD5
      • Up to 6.4 Gbps IPSec and 3 Gbps Air
        Ciphering
    • Ethernet Subsystem
      • Eight SGMII Ports with Wire Rate Switching
      • IEEE1588 v2 (with Annex D/E/F) Support
      • 8 Gbps Total Ingress/Egress Ethernet BW
        from Core
      • Audio/Video Bridging (802.1Qav/D6.0)
      • QOS Capability
      • DSCP Priority Mapping
  • Peripherals
    • Two PCIe Gen2 Controllers with Support for
      • Two Lanes per Controller
      • Supports Up to 5 GBaud
    • One HyperLink
      • Supports Connections to Other KeyStone Architecture
        Devices Providing Resource
        Scalability
      • Supports Up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem
      • Two SGMII/XFI Ports with Wire Rate
        Switching and MACSEC Support
      • IEEE1588 v2 (with Annex D/E/F) Support
    • One 72-Bit DDR3/DDR3L Interface with Speeds Up
      to 1600 MTPS in DDR3 Mode
    • EMIF16 Interface
    • Two USB 2.0/3.0 Controllers
    • USIM Interface
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • One TSIP
      • Support 1024 DS0s
      • Support 2 Lanes at 32.768/16.3848.192
        Mbps Per Lane
  • System Resources
    • Three On-Chip PLLs
    • SmartReflex Automatic Voltage Scaling
    • Semaphore Module
    • Twelve 64-Bit Timers
    • Five Enhanced Direct Memory Access (EDMA)
      Modules
  • Commercial Case Temperature:
    • 0°C to 85°C
  • Extended Case Temperature:
    • –40°C to 100°C
open-in-new Find other Arm-based processors

The AM5K2E0x is a high performance device based on TI’s KeyStone II Multicore SoC Architecture, incorporating the most performance-optimized Cortex-A15 processor dual-core or quad-core CorePac that can run at a core speed of up to 1.4 GHz. TI’s AM5K2E0x device enables a high performance, power-efficient and easy to use platform for developers of a broad range of applications such as enterprise grade networking end equipment, data center networking, avionics and defense, medical imaging, test and automation.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (for example, ARM CorePac (Cortex-A15 Processor Quad Core CorePac), network processing, and uses a queue-based communication system that allows the device resources to operate efficiently and seamlessly. This unique device architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

The AM5K2E0x KeyStone II device integrates a large amount of on-chip memory. The Cortex-A15 processor cores each have 32KB of L1Data and 32KB of L1 Instruction cache. The up to four Cortex A15 cores in the ARM CorePac share a 4MB L2 Cache. The device also integrates 2MB of Multicore Shared Memory (MSMC) that can be used as a shared L3 SRAM. All L2 and MSMC memories incorporate error detection and error correction. For fast access to external memory, this device includes a 64-bit DDR-3 (72-bit with ECC support) external memory interface (EMIF) running at 1600 MTPS.

The device enables developers to use a variety of development and debugging tools that include GNU GCC, GDB, Open source Linux, Eclipse based debugging environment enabling kernel and user space debugging using a variety of Eclipse plug-ins including TI's industry leading IDE Code Composer Studio.

The AM5K2E0x is a high performance device based on TI’s KeyStone II Multicore SoC Architecture, incorporating the most performance-optimized Cortex-A15 processor dual-core or quad-core CorePac that can run at a core speed of up to 1.4 GHz. TI’s AM5K2E0x device enables a high performance, power-efficient and easy to use platform for developers of a broad range of applications such as enterprise grade networking end equipment, data center networking, avionics and defense, medical imaging, test and automation.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (for example, ARM CorePac (Cortex-A15 Processor Quad Core CorePac), network processing, and uses a queue-based communication system that allows the device resources to operate efficiently and seamlessly. This unique device architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

The AM5K2E0x KeyStone II device integrates a large amount of on-chip memory. The Cortex-A15 processor cores each have 32KB of L1Data and 32KB of L1 Instruction cache. The up to four Cortex A15 cores in the ARM CorePac share a 4MB L2 Cache. The device also integrates 2MB of Multicore Shared Memory (MSMC) that can be used as a shared L3 SRAM. All L2 and MSMC memories incorporate error detection and error correction. For fast access to external memory, this device includes a 64-bit DDR-3 (72-bit with ECC support) external memory interface (EMIF) running at 1600 MTPS.

The device enables developers to use a variety of development and debugging tools that include GNU GCC, GDB, Open source Linux, Eclipse based debugging environment enabling kernel and user space debugging using a variety of Eclipse plug-ins including TI's industry leading IDE Code Composer Studio.

open-in-new Find other Arm-based processors
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Technical documentation

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Type Title Date
* Data sheet AM5K2E04/02 Multicore ARM KeyStone II System-on-Chip (SoC) datasheet (Rev. D) 11 Mar 2015
* Errata AM5K2E04/02 KeyStone SoC Silicon Errata (Silicon Rev 1.0) (Rev. B) 20 Aug 2015
Application note Using Arm ROM Bootloader on Keystone II Devices 04 Jun 2019
Application note Keystone Multicore Device Family Schematic Checklist 17 May 2019
Application note KeyStone II DDR3 interface bring-up 07 Mar 2019
Technical article Bringing the next evolution of machine learning to the edge 27 Nov 2018
User guide How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS 24 Sep 2018
Technical article How quality assurance on the Processor SDK can improve software scalability 22 Aug 2018
Application note DDR3 Design Requirements for KeyStone Devices (Rev. C) 23 Jan 2018
User guide KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) (Rev. A) 21 Aug 2017
Application note Thermal Design Guide for DSP and Arm Application Processors (Rev. B) 14 Aug 2017
User guide Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I) 26 Jul 2017
Application note Power Consumption Summary for K2E System-on-Chip (SoC) Device Family 14 Jun 2017
Selection guide TI Components for Aerospace and Defense Guide (Rev. E) 22 Mar 2017
Application note Clocking Spreadsheet for K2E Device Family 26 Jan 2017
User guide Serializer/Deserializer (SerDes) for KeyStone II Devices User Guide (Rev. A) 27 Jul 2016
Technical article Clove: Low-Power video solutions based on Sitara™ AM57x processors 21 Jul 2016
Application note Power Management of KS2 Device (Rev. C) 15 Jul 2016
Technical article Spring has sprung. A sale has sprung. 04 Apr 2016
Application note Throughput Performance Guide for KeyStone II Devices (Rev. B) 22 Dec 2015
Application note Keystone II DDR3 Debug Guide 16 Oct 2015
User guide Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B) 06 May 2015
User guide Gigabit Ethernet (GbE) Switch SS for K2E & K2L Devices User's Guide (Rev. A) 28 Apr 2015
User guide Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H) 09 Apr 2015
User guide DDR3 Memory Controller for KeyStone II Devices User's Guide (Rev. C) 27 Mar 2015
White paper Save power and costs with TI's K2E on-chip networking features 25 Mar 2015
Application note Keystone II DDR3 Initialization 26 Jan 2015
User guide Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C) 04 Sep 2014
White paper KeyStone™-II-based processors: 10G Ethernet as an optical interface 25 Aug 2014
User guide Packet Accelerator 2 (PA2) for K2E and K2L Devices User's Guide 19 Aug 2014
User guide Security Accelerator 2 (SA2) for K2E and K2L Devices User's Guide 19 Aug 2014
White paper Differentiating AM5K2E02 and AM5K2E04 SoCs from Alternate ARM® Cortex®-A15 Devic 14 Aug 2014
User guide Network Coprocessor (NETCP) for K2E and K2L Devices User's Guide 13 Aug 2014
Application note Hardware Design Guide for KeyStone II Devices 24 Mar 2014
User guide PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D) 30 Sep 2013
User guide Debug and Trace for KeyStone II Devices User's Guide 26 Jul 2013
User guide ARM Bootloader User Guide for KeyStone II Devices 21 Jul 2013
User guide Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A) 28 Jun 2013
User guide HyperLink for KeyStone Devices User's Guide (Rev. C) 28 May 2013
User guide Multicore Shared Memory Controller (MSMC) User Guide for KeyStone II Devices 12 Nov 2012
More literature Industrial Imaging: Applications of the K2H and K2E platforms 09 Nov 2012
More literature Video Infrastructure - Applications of the K2E, K2H platforms 09 Nov 2012
More literature OpenMP Programming for TMS320C66x Multicore DSPs (Rev. A) 05 Nov 2012
User guide ARM CorePac User Guide for KeyStone II Devices 31 Oct 2012
Application note Multicore Programming Guide (Rev. B) 29 Aug 2012
User guide Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A) 30 Mar 2012
User guide Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A) 27 Mar 2012
User guide 64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A) 22 Mar 2012
Application note PCIe Use Cases for KeyStone Devices 13 Dec 2011
User guide Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide 02 Sep 2011
User guide External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A) 24 May 2011
User guide C66x DSP Cache User's Guide 09 Nov 2010
Application note Clocking Design Guide for KeyStone Devices 09 Nov 2010
User guide General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide 09 Nov 2010
Application note Optimizing Loops on the C66x DSP 09 Nov 2010
User guide Telecom Serial Interface Port (TSIP) for KeyStone Devices User's Guide 09 Nov 2010
User guide Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG 09 Nov 2010

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

EINFO-3P-SOM-EVM — eInfochips System on Modules and EVMs

eInfochips is a product engineering and design services company with over 20 years of experience, 500+ product developments, and over 40M deployments in 140 countries, across the world. The company has delivered turnkey technology solutions for many Fortune 500 companies, across multiple verticals (...)

From: eInfochips
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Debug probe

TMDSEMU200-U — XDS200 USB Debug Probe

The XDS200 is a debug probe (emulator) used for debugging TI embedded devices.  The XDS200 features a balance of low cost with good performance as compared to the low cost XDS110 and the high performance XDS560v2.  It supports a wide variety of standards (IEEE1149.1, IEEE1149.7, SWD) in a (...)

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Limit: 3
Debug probe

TMDSEMU560V2STM-U — XDS560v2 System Trace USB Debug Probe

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

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Debug probe

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB & Ethernet Debug Probe

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

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Development kit

EVMK2EX — K2E Development Board

The EVMK2EX is a full-featured development tool for 66AK2Exx and AM5K2Exx KeyStone II based SoCs. Get started developing general purpose embedded computing systems for industrial, mission critical, and networking applications today with this double-wide AMC form-factor evaluation board featuring a (...)

document-pdfAcrobat User guide
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Software development kit (SDK)

PROCESSOR-SDK-K2E — Processor SDK for 66AK2Ex Processors - Linux and TI-RTOS support

 

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

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IDE, configuration, compiler or debugger

CCSTUDIO-KEYSTONE — Code Composer Studio (CCS) Integrated Development Environment (IDE) for Multicore Processors

Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor (...)

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Operating system (OS)

HCCE-3P-RTOS-COMPONENTS — HCC Embedded TI-RTOS software

For more than a decade HCC has focused on developing re-usable embedded software components for Flash, file systems and communications. Many of the leading RTOS vendors in the industry re-sell HCC software under their own brand, giving engineers access to excellent middleware regardless of the RTOS (...)
From: HCC-Embedded
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Simulation model

AM5K2E04 AM5K2E02 ABD IBIS Model

SPRM621.ZIP (2180 KB) - IBIS Model
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Simulation model

AM5K2E04 AM5K2E02 ABD Thermal Model

SPRM622.ZIP (5 KB) - Thermal Model
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Simulation model

AM5K2E04 AM5K2E02 ABD BSDL Model

SPRM623.ZIP (28 KB) - BSDL Model
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Simulation model

AM5K2E04 and AM5K2E02 Power Consumption Model (Rev. A)

SPRM653A.ZIP (142 KB) - Power Model
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Simulation model

KeyStone II IBIS AMI Models

SPRM743.ZIP (265889 KB) - IBIS-AMI Model
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Calculation tool

CLOCKTREETOOL — Clock Tree Tool for Sitara, Automotive, Vision Analytics, & Digital Signal Processors

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:
  • Visualize the device clock tree
  • Interact with clock tree elements (...)
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Design tool

PROCESSORS-3P-SEARCH — Arm-based MPU, arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
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Schematic

66AK2E05 66AK2E02 AM5K2E04 AM5K2E02 ABD OrCAD Symbols

SPRR197.ZIP (99 KB)
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Reference designs

TIDEP0042 — Generating AVS SmartReflex Core Voltage for K2E Using TPS544C25 and PMBus Reference Design

The K2E requires the use of AVS SmartReflex control for the CVDD core voltage. This design provides method of generating the proper voltage using software and the PMBus interface of the TPS544C25. The circuit can be implemented on the XEVMK2EX.
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Reference designs

TIDEP0041 — Generating AVS SmartReflex core voltage, PMBus for K2E reference design

The K2E requires the use of AVS SmartReflex control for the CVDD core voltage. This design provides method of generating the proper voltage without the need for any software. The circuit is currently implemented on the XEVMK2EX.
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Reference designs

TIDEP0031 — Power Sequencing for K2E Using UCD9090 with PMBus

The K2E devices require power supplies to be sequenced in a proper order. This design demonstrates power sequencing for the 66AK2Ex and AM5K2Ex families of KeyStone II ARM+DSP and ARM-only multicore processors by use of the UCD9090. The UCD9090 is a 10-rail PMBus/I2C addressable power-supply (...)
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Reference designs

TIDEP0026 — K2E Clock Generation Reference Design

A single clock source should not be used to drive multiple clock inputs for a high-performance processor device, such as multicore ARM Cortex-A15 based 66AK2Ex and AM5K2Ex processors, since excessive loading, reflections, and noise will negatively impact performance. These can be avoided through the (...)
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Ordering & quality

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  • MSL rating/Peak reflow
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  • Ongoing reliability monitoring

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