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AM5K2E02

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Sitara processor: dual-Arm Cortex-A15

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Data sheet

AM5K2E02

ACTIVE
Data sheet Order now

Product details

CPU 2 Arm Cortex-A15 Frequency (MHz) 1250, 1400 Protocols Ethernet PCIe 4 PCIe Gen 2 Hardware accelerators Packet Accelerator, Security Accelerator Features Networking Operating system Linux, RTOS Rating Catalog Operating temperature range (°C) -40 to 100
CPU 2 Arm Cortex-A15 Frequency (MHz) 1250, 1400 Protocols Ethernet PCIe 4 PCIe Gen 2 Hardware accelerators Packet Accelerator, Security Accelerator Features Networking Operating system Linux, RTOS Rating Catalog Operating temperature range (°C) -40 to 100
FCBGA (ABD) 1089 729 mm² (27 mm × 27 mm)
  • ARM® Cortex®-A15 MPCore™ CorePac
    • Up to Four ARM Cortex-A15 Processor Cores at
      up to 1.4-GHz
    • 4MB L2 Cache Memory Shared by all Cortex-
      A15 Processor Cores
    • Full Implementation of ARMv7-A Architecture
      Instruction Set
    • 32KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE)
      Master Port, Connected to MSMC (Multicore
      Shared Memory Controller) for Low Latency
      Access to SRAM and DDR3
  • Multicore Shared Memory Controller (MSMC)
    • 2 MB SRAM Memory for ARM CorePac
    • Memory Protection Unit for Both SRAM and
      DDR3_EMIF
  • Multicore Navigator
    • 8k Multi-Purpose Hardware Queues with Queue
      Manager
    • One Packet-Based DMA Engine for Zero-
      Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP,
        PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1 Gbps Wire Speed Throughput at 1.5
        MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP and WiMAX Air
        Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM,
        HMAC, CMAC, GMAC, AES, DES, 3DES,
        Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit
        Hash), MD5
      • Up to 6.4 Gbps IPSec and 3 Gbps Air
        Ciphering
    • Ethernet Subsystem
      • Eight SGMII Ports with Wire Rate Switching
      • IEEE1588 v2 (with Annex D/E/F) Support
      • 8 Gbps Total Ingress/Egress Ethernet BW
        from Core
      • Audio/Video Bridging (802.1Qav/D6.0)
      • QOS Capability
      • DSCP Priority Mapping
  • Peripherals
    • Two PCIe Gen2 Controllers with Support for
      • Two Lanes per Controller
      • Supports Up to 5 GBaud
    • One HyperLink
      • Supports Connections to Other KeyStone Architecture
        Devices Providing Resource
        Scalability
      • Supports Up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem
      • Two SGMII/XFI Ports with Wire Rate
        Switching and MACSEC Support
      • IEEE1588 v2 (with Annex D/E/F) Support
    • One 72-Bit DDR3/DDR3L Interface with Speeds Up
      to 1600 MTPS in DDR3 Mode
    • EMIF16 Interface
    • Two USB 2.0/3.0 Controllers
    • USIM Interface
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • One TSIP
      • Support 1024 DS0s
      • Support 2 Lanes at 32.768/16.3848.192
        Mbps Per Lane
  • System Resources
    • Three On-Chip PLLs
    • SmartReflex Automatic Voltage Scaling
    • Semaphore Module
    • Twelve 64-Bit Timers
    • Five Enhanced Direct Memory Access (EDMA)
      Modules
  • Commercial Case Temperature:
    • 0°C to 85°C
  • Extended Case Temperature:
    • –40°C to 100°C
  • ARM® Cortex®-A15 MPCore™ CorePac
    • Up to Four ARM Cortex-A15 Processor Cores at
      up to 1.4-GHz
    • 4MB L2 Cache Memory Shared by all Cortex-
      A15 Processor Cores
    • Full Implementation of ARMv7-A Architecture
      Instruction Set
    • 32KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE)
      Master Port, Connected to MSMC (Multicore
      Shared Memory Controller) for Low Latency
      Access to SRAM and DDR3
  • Multicore Shared Memory Controller (MSMC)
    • 2 MB SRAM Memory for ARM CorePac
    • Memory Protection Unit for Both SRAM and
      DDR3_EMIF
  • Multicore Navigator
    • 8k Multi-Purpose Hardware Queues with Queue
      Manager
    • One Packet-Based DMA Engine for Zero-
      Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP,
        PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1 Gbps Wire Speed Throughput at 1.5
        MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP and WiMAX Air
        Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM,
        HMAC, CMAC, GMAC, AES, DES, 3DES,
        Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit
        Hash), MD5
      • Up to 6.4 Gbps IPSec and 3 Gbps Air
        Ciphering
    • Ethernet Subsystem
      • Eight SGMII Ports with Wire Rate Switching
      • IEEE1588 v2 (with Annex D/E/F) Support
      • 8 Gbps Total Ingress/Egress Ethernet BW
        from Core
      • Audio/Video Bridging (802.1Qav/D6.0)
      • QOS Capability
      • DSCP Priority Mapping
  • Peripherals
    • Two PCIe Gen2 Controllers with Support for
      • Two Lanes per Controller
      • Supports Up to 5 GBaud
    • One HyperLink
      • Supports Connections to Other KeyStone Architecture
        Devices Providing Resource
        Scalability
      • Supports Up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem
      • Two SGMII/XFI Ports with Wire Rate
        Switching and MACSEC Support
      • IEEE1588 v2 (with Annex D/E/F) Support
    • One 72-Bit DDR3/DDR3L Interface with Speeds Up
      to 1600 MTPS in DDR3 Mode
    • EMIF16 Interface
    • Two USB 2.0/3.0 Controllers
    • USIM Interface
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • One TSIP
      • Support 1024 DS0s
      • Support 2 Lanes at 32.768/16.3848.192
        Mbps Per Lane
  • System Resources
    • Three On-Chip PLLs
    • SmartReflex Automatic Voltage Scaling
    • Semaphore Module
    • Twelve 64-Bit Timers
    • Five Enhanced Direct Memory Access (EDMA)
      Modules
  • Commercial Case Temperature:
    • 0°C to 85°C
  • Extended Case Temperature:
    • –40°C to 100°C

The AM5K2E0x is a high performance device based on TI’s KeyStone II Multicore SoC Architecture, incorporating the most performance-optimized Cortex-A15 processor dual-core or quad-core CorePac that can run at a core speed of up to 1.4 GHz. TI’s AM5K2E0x device enables a high performance, power-efficient and easy to use platform for developers of a broad range of applications such as enterprise grade networking end equipment, data center networking, avionics and defense, medical imaging, test and automation.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (for example, ARM CorePac (Cortex-A15 Processor Quad Core CorePac), network processing, and uses a queue-based communication system that allows the device resources to operate efficiently and seamlessly. This unique device architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

The AM5K2E0x KeyStone II device integrates a large amount of on-chip memory. The Cortex-A15 processor cores each have 32KB of L1Data and 32KB of L1 Instruction cache. The up to four Cortex A15 cores in the ARM CorePac share a 4MB L2 Cache. The device also integrates 2MB of Multicore Shared Memory (MSMC) that can be used as a shared L3 SRAM. All L2 and MSMC memories incorporate error detection and error correction. For fast access to external memory, this device includes a 64-bit DDR-3 (72-bit with ECC support) external memory interface (EMIF) running at 1600 MTPS.

The device enables developers to use a variety of development and debugging tools that include GNU GCC, GDB, Open source Linux, Eclipse based debugging environment enabling kernel and user space debugging using a variety of Eclipse plug-ins including TI's industry leading IDE Code Composer Studio.

The AM5K2E0x is a high performance device based on TI’s KeyStone II Multicore SoC Architecture, incorporating the most performance-optimized Cortex-A15 processor dual-core or quad-core CorePac that can run at a core speed of up to 1.4 GHz. TI’s AM5K2E0x device enables a high performance, power-efficient and easy to use platform for developers of a broad range of applications such as enterprise grade networking end equipment, data center networking, avionics and defense, medical imaging, test and automation.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (for example, ARM CorePac (Cortex-A15 Processor Quad Core CorePac), network processing, and uses a queue-based communication system that allows the device resources to operate efficiently and seamlessly. This unique device architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

The AM5K2E0x KeyStone II device integrates a large amount of on-chip memory. The Cortex-A15 processor cores each have 32KB of L1Data and 32KB of L1 Instruction cache. The up to four Cortex A15 cores in the ARM CorePac share a 4MB L2 Cache. The device also integrates 2MB of Multicore Shared Memory (MSMC) that can be used as a shared L3 SRAM. All L2 and MSMC memories incorporate error detection and error correction. For fast access to external memory, this device includes a 64-bit DDR-3 (72-bit with ECC support) external memory interface (EMIF) running at 1600 MTPS.

The device enables developers to use a variety of development and debugging tools that include GNU GCC, GDB, Open source Linux, Eclipse based debugging environment enabling kernel and user space debugging using a variety of Eclipse plug-ins including TI's industry leading IDE Code Composer Studio.
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Technical documentation

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* Data sheet AM5K2E04/02 Multicore ARM KeyStone II System-on-Chip (SoC) datasheet (Rev. D) Mar 11, 2015
* Errata AM5K2E04/02 KeyStone SoC Silicon Errata (Silicon Rev 1.0) (Rev. B) Aug 20, 2015
Application note DDR3 Design Requirements for KeyStone Devices (Rev. D) PDF | HTML Jul 7, 2022
Application note Using Arm ROM Bootloader on Keystone II Devices PDF | HTML Jun 4, 2019
Application note Keystone Multicore Device Family Schematic Checklist PDF | HTML May 17, 2019
Application note KeyStone II DDR3 interface bring-up PDF | HTML Mar 7, 2019
User guide How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS Sep 24, 2018
User guide KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) (Rev. A) Aug 21, 2017
Application note Thermal Design Guide for DSP and Arm Application Processors (Rev. B) Aug 14, 2017
User guide Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I) Jul 26, 2017
Application note Power Consumption Summary for K2E System-on-Chip (SoC) Device Family Jun 14, 2017
Application note Clocking Spreadsheet for K2E Device Family Jan 26, 2017
User guide Serializer/Deserializer (SerDes) for KeyStone II Devices User Guide (Rev. A) Jul 27, 2016
Application note Power Management of KS2 Device (Rev. C) Jul 15, 2016
Application note Throughput Performance Guide for KeyStone II Devices (Rev. B) Dec 22, 2015
Application note Keystone II DDR3 Debug Guide Oct 16, 2015
User guide Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B) PDF | HTML May 6, 2015
User guide Gigabit Ethernet (GbE) Switch SS for K2E & K2L Devices User's Guide (Rev. A) Apr 28, 2015
User guide Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H) PDF | HTML Apr 9, 2015
User guide DDR3 Memory Controller for KeyStone II Devices User's Guide (Rev. C) Mar 27, 2015
White paper Save power and costs with TI's K2E on-chip networking features Mar 25, 2015
Application note Keystone II DDR3 Initialization Jan 26, 2015
User guide Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C) Sep 4, 2014
White paper KeyStone™-II-based processors: 10G Ethernet as an optical interface Aug 25, 2014
User guide Security Accelerator 2 (SA2) for K2E and K2L Devices User's Guide Aug 19, 2014
User guide Packet Accelerator 2 (PA2) for K2E and K2L Devices User's Guide Aug 19, 2014
White paper Differentiating AM5K2E02 and AM5K2E04 SoCs from Alternate ARM® Cortex®-A15 Devic Aug 14, 2014
User guide Network Coprocessor (NETCP) for K2E and K2L Devices User's Guide Aug 13, 2014
Application note Hardware Design Guide for KeyStone II Devices Mar 24, 2014
User guide PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D) Sep 30, 2013
User guide Debug and Trace for KeyStone II Devices User's Guide Jul 26, 2013
User guide ARM Bootloader User Guide for KeyStone II Devices Jul 21, 2013
User guide Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A) Jun 28, 2013
User guide HyperLink for KeyStone Devices User's Guide (Rev. C) May 28, 2013
User guide Multicore Shared Memory Controller (MSMC) User Guide for KeyStone II Devices Nov 12, 2012
Product overview Industrial Imaging: Applications of the K2H and K2E platforms Nov 9, 2012
Product overview Video Infrastructure - Applications of the K2E, K2H platforms Nov 9, 2012
Product overview OpenMP Programming for TMS320C66x Multicore DSPs (Rev. A) Nov 5, 2012
User guide ARM CorePac User Guide for KeyStone II Devices Oct 31, 2012
Application note Multicore Programming Guide (Rev. B) Aug 29, 2012
User guide Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A) Mar 30, 2012
User guide Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A) Mar 27, 2012
User guide 64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A) Mar 22, 2012
Application note PCIe Use Cases for KeyStone Devices Dec 13, 2011
User guide Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide Sep 2, 2011
User guide External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A) May 24, 2011
Application note Optimizing Loops on the C66x DSP Nov 9, 2010
User guide General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide Nov 9, 2010
Application note Clocking Design Guide for KeyStone Devices Nov 9, 2010
User guide Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG Nov 9, 2010
User guide C66x DSP Cache User's Guide Nov 9, 2010
User guide Telecom Serial Interface Port (TSIP) for KeyStone Devices User's Guide Nov 9, 2010

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Development kit

EVMK2EX — K2E Development Board

The EVMK2EX is a full-featured development tool for 66AK2Exx and AM5K2Exx KeyStone II based SoCs. Get started developing general purpose embedded computing systems for industrial, mission critical, and networking applications today with this double-wide AMC form-factor evaluation board featuring a (...)

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Debug probe

TMDSEMU200-U — XDS200 USB Debug Probe

The XDS200 is a debug probe (emulator) used for debugging TI embedded devices. For the majority of devices it is recommended to use the newer, lower cost XDS110 (www.ti.com/tool/TMDSEMU110-U). The XDS200 supports a wide variety of standards (IEEE1149.1, IEEE1149.7, SWD) in a single pod. All XDS (...)

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Debug probe

TMDSEMU560V2STM-U — XDS560™ software v2 system trace USB debug probe

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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In stock
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Debug probe

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB & Ethernet Debug Probe

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

Supported products & hardware
In stock
Limit:
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Software development kit (SDK)

BIOSLINUXMCSDK-K2 — MCSDK supporting SYS/BIOS RTOS and Linux OS for KeyStone II ARM A15 + DSP C66x

NOTE: K2x, C665x and C667x devices are now actively maintained on the Processor-SDK release stream. See links above.

Our Multicore Software Development Kits (MCSDK) provide highly-optimized bundles of foundational, platform-specific drivers to enable development on selected TI ARM and DSP devices. (...)

Supported products & hardware
Software development kit (SDK)

PROCESSOR-SDK-LINUX-K2E — Linux Processor SDK for K2E

 

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

Supported products & hardware
Software development kit (SDK)

PROCESSOR-SDK-LINUX-RT-K2E — Linux-RT Processor SDK for K2E

 

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

Supported products & hardware
Software development kit (SDK)

PROCESSOR-SDK-RTOS-K2E — RTOS Processor SDK for K2E

 

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

Supported products & hardware
IDE, configuration, compiler or debugger

CCSTUDIO — CCStudio™ IDE

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

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Simulation model

AM5K2E04 AM5K2E02 ABD BSDL Model

SPRM623.ZIP (28 KB) - BSDL model
Supported products & hardware
Simulation model

AM5K2E04 AM5K2E02 ABD IBIS Model

SPRM621.ZIP (2180 KB) - IBIS model
Supported products & hardware
Simulation model

AM5K2E04 AM5K2E02 ABD Thermal Model

SPRM622.ZIP (5 KB) - Thermal model
Supported products & hardware
Simulation model

AM5K2E04 and AM5K2E02 Power Consumption Model (Rev. A)

SPRM653A.ZIP (142 KB) - Power model
Supported products & hardware
Simulation model

KeyStone II IBIS AMI Models

SPRM743.ZIP (265889 KB) - IBIS-AMI model
lock = Requires export approval (1 minute)
Supported products & hardware
Calculation tool

CLOCKTREETOOL — Clock Tree Tool for Sitara, Automotive, Vision Analytics, & Digital Signal Processors


The Clock Tree Tool (CTT) for ARM Processors & Digital Signal Processors is an interactive configuration software tool that provides information about device clock tree architecture. This tool allows visualization of the device clock tree. It can also be used to determine the exact register (...)

Supported products & hardware
Reference design

TIDEP0026 — K2E Clock Generation Reference Design

A single clock source should not be used to drive multiple clock inputs for a high-performance processor device, such as multicore ARM Cortex-A15 based 66AK2Ex and AM5K2Ex processors, since excessive loading, reflections, and noise will negatively impact performance. These can be avoided through (...)

Supported products & hardware
Reference design

TIDEP0031 — Power Sequencing for K2E Using UCD9090 with PMBus

The K2E devices require power supplies to be sequenced in a proper order. This design demonstrates power sequencing for the 66AK2Ex and AM5K2Ex families of KeyStone II ARM+DSP and ARM-only multicore processors by use of the UCD9090. The UCD9090 is a 10-rail PMBus/I2C addressable power-supply (...)

Supported products & hardware
Reference design

TIDEP0041 — Generating AVS SmartReflex core voltage, PMBus for K2E reference design

The K2E requires the use of AVS SmartReflex control for the CVDD core voltage. This design provides method of generating the proper voltage without the need for any software. The circuit is currently implemented on the XEVMK2EX.

Supported products & hardware
Reference design

TIDEP0042 — Generating AVS SmartReflex Core Voltage for K2E Using TPS544C25 and PMBus Reference Design

The K2E requires the use of AVS SmartReflex control for the CVDD core voltage. This design provides method of generating the proper voltage using software and the PMBus interface of the TPS544C25. The circuit can be implemented on the XEVMK2EX.

Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
FCBGA (ABD) 1089 Ultra Librarian
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Ordering & quality

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

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