TIDEP0079

EtherCAT® Reference Design on Sitara AM57x Gb Ethernet and PRU-ICSS with Time Triggered Send

TIDEP0079

Design files

Overview

The TIDEP0079 reference design demonstrates an EtherCAT® master interface running on the Sitara™ AM572x processor using the EC-Master stack from acontis. This EtherCAT master solution can be used for EtherCAT-based PLC or motion control applications. EtherCAT master is profiled on both the Ethernet switch and the PRU-ICSS Ethernet ports of the AM572x processor to give designers flexibility to use any of the two switch ports or four PRU-ICSS Ethernet ports on the device. The EtherCAT master implementation can achieve less than 100µs cycle times for both the switch and the PRU-ICSS Ethernet ports. Time-triggered send (TTS) can be enabled on the PRU-ICSS to reduce jitter, achieve shorter cycle times, and reduce latency in cases where distributed clocking is not used.

Features
  • Examples for implementing EtherCAT master on both the Ethernet switch (CPSW) and the PRU-ICSS Ethernet ports for design flexibility
  • EtherCAT master on PRU-ICSS featuring Time Triggered Send
  • Highly portable acontis EC-Master stack
  • Cycle CPU consumption of less than 30µs is achieved for both the Ethernet switch and PRU-ICSS Ethernet ports
  • EtherCAT class A or class B master stack according to ETG.1500 specification
  • This reference design is tested on the TMDXIDK5728 board and includes documentation, software, demo application, and HW design files

A fully assembled board has been developed for testing and performance validation only, and is not available for sale.

Design files & products

Design files

Download ready-to-use system files to speed your design process.

TIDUBZ1B.PDF (2490 K)

Reference design overview and verified performance test data

TIDRLH4.ZIP (1453 K)

Detailed schematic diagram for design layout and components

TIDRLH5.ZIP (31 K)

Complete listing of design components, reference designators, and manufacturers/part numbers

TIDRLH6.ZIP (606 K)

Detailed overview of design layout for component placement

TIDRLH7A.PDF (6325 K)

Files used for 3D models or 2D drawings of IC components

TIDRLH7.ZIP (19060 K)

Files used for 3D models or 2D drawings of IC components

TIDCC42A.ZIP (1495 K)

Design file that contains information on physical board layer of design PCB

TIDCC42.ZIP (10113 K)

Design file that contains information on physical board layer of design PCB

Products

Includes TI products in the design and potential alternatives.

Arm-based processors

AM5716Sitara processor: Arm Cortex-A15 & DSP

Data sheet document-pdfAcrobat PDF open-in-new HTML
Arm-based processors

AM5718Sitara processor: Arm Cortex-A15 & DSP, multimedia

Data sheet document-pdfAcrobat PDF open-in-new HTML
Arm-based processors

AM5726Sitara processor: dual Arm Cortex-A15 & dual DSP

Data sheet document-pdfAcrobat PDF open-in-new HTML
Arm-based processors

AM5728Sitara processor: dual Arm Cortex-A15 & dual DSP, multimedia

Data sheet document-pdfAcrobat PDF open-in-new HTML
Clock generators

CDCE913Programmable 1-PLL VCXO clock synthesizer with 2.5-V or 3.3-V LVCMOS outputs

Data sheet document-pdfAcrobat PDF open-in-new HTML
Ethernet PHYs

TLK105LIndustrial temperature, single port 10/100-Mbps Ethernet physical layer

Data sheet document-pdfAcrobat PDF open-in-new HTML
Multi-channel ICs (PMICs)

TPS659037Power Management IC (PMIC) for ARM Cortex A15 Processors

Data sheet document-pdfAcrobat PDF open-in-new HTML
Noninverting buffers & drivers

SN74LVC1G07Single 1.65-V to 5.5-V buffer with open-drain outputs

Data sheet document-pdfAcrobat PDF open-in-new HTML
RS-485 & RS-422 transceivers

SN65HVD783.3 V Half-Duplex RS-485, with IEC ESD, 50 Mbps

Data sheet document-pdfAcrobat PDF open-in-new HTML

Technical documentation

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* Design guide TIDEP0079 Design Guide (Rev. B) Oct. 26, 2016
Technical article Rise of the industrial robots. Overcoming the challenges of safe robot-human-interaction in factory automation Nov. 08, 2016

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