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TPS659037

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Power Management IC (PMIC) for ARM Cortex A15 Processors

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TPS659037

ACTIVE
Data sheet Order now

Product details

Processor supplier Texas Instruments Processor name Sitara AM57x Regulated outputs (#) 14 Step-down DC/DC converter 7 Step-up DC/DC converter 0 LDO 7 Vin (min) (V) 3.135 Vin (max) (V) 5.25 Vout (min) (V) 0.7 Vout (max) (V) 3.3 Iout (max) (A) 6 Configurability Factory programmable, Software configurable Features Comm control, Power good, Power sequencing Rating Automotive, Catalog Operating temperature range (°C) -40 to 85 Step-down DC/DC controller 0 Step-up DC/DC controller 0 Iq (typ) (mA) 0.15 Switching frequency (max) (kHz) 2700 Shutdown current (ISD) (typ) (µA) 20 Switching frequency (typ) (kHz) 2200 Product type Processor and FPGA
Processor supplier Texas Instruments Processor name Sitara AM57x Regulated outputs (#) 14 Step-down DC/DC converter 7 Step-up DC/DC converter 0 LDO 7 Vin (min) (V) 3.135 Vin (max) (V) 5.25 Vout (min) (V) 0.7 Vout (max) (V) 3.3 Iout (max) (A) 6 Configurability Factory programmable, Software configurable Features Comm control, Power good, Power sequencing Rating Automotive, Catalog Operating temperature range (°C) -40 to 85 Step-down DC/DC controller 0 Step-up DC/DC controller 0 Iq (typ) (mA) 0.15 Switching frequency (max) (kHz) 2700 Shutdown current (ISD) (typ) (µA) 20 Switching frequency (typ) (kHz) 2200 Product type Processor and FPGA
NFBGA (ZWS) 169 144 mm² 12 x 12
  • Seven Step-Down Switched-Mode Power Supply (SMPS) Regulators:
    • One 0.7 to 1.65 V at 6 A (10-mV Steps)
      • Dual-Phase Configuration With Digital Voltage Scaling (DVS) Control
    • One 0.7 to 1.65 V at 4 A (10-mV Steps)
      • Dual-Phase Configuration With DVS Control
    • One 0.7 to 3.3 V at 3 A (10 or 20-mV Steps)
      • Single-Phase Configuration
      • This Regulator can be Combined With the 6 A Resulting in a 9-A Triple-Phase Regulator (DVS Controlled)
    • Two 0.7 to 3.3 V at 2 A (10 or 20-mV Steps)
      • Single-Phase Configuration
      • One Regulator With DVS Control That can also be Configured as a 3-A Regulator
    • Two 0.7 to 3.3 V at 1 A (10 or 20-mV Steps)
      • Single-Phase Configuration
      • One Regulator With DVS Control
    • Output Current Measurement in All Except 1-A SMPS Regulators
    • Differential Remote Sensing (Output and Ground) in Dual-Phase and Triple-Phase Regulators
    • Hardware and Software-Controlled Eco-mode™ up to 5 mA with 15-µA Quiescent Current
    • Short-Circuit Protection
    • Powergood Indication (Voltage and Overcurrent Indication)
    • Internal Soft-Start for In-Rush Current Limitation
    • Ability to synchronize SMPS to External Clock or Internal Fallback Clock With Phase Synchronization
  • Seven General-Purpose Low Dropout Regulators (LDOs) with 50-mV Steps:
    • Two 0.9 to 3.3-V LDOs at 300 mA With Preregulated Supply
    • Two 0.9 to 3.3-V LDOs at 200 mA With Preregulated Supply
    • One 0.9 to 3.3-V LDOs at 50 mA With Preregulated Supply
    • One 100-mA USB LDO
    • One 0.9 to 3.3-V, Low-Noise LDO up to 100 mA (Low-Noise Performance up to 50 mA)
    • Two Additional LDOs for PMU Internal Use
    • Short-Circuit Protection
  • Clock Management 16-MHz Crystal Oscillator and 32-kHz RC Oscillator
    • One Buffered 32-kHz Output
  • Real-Time Clock (RTC) With Alarm Wake-Up Mechanism
  • 12-bit Sigma-Delta General-Purpose Analog-to-Digital-Converter (GPADC) With Three External Input Channels and Six Internal Channels for Self Monitoring
  • Thermal Monitoring
    • High Temperature Warning
    • Thermal Shutdown
  • Control
    • Configurable Power-Up and Power-Down Sequences (One-Time Programmable [OTP])
    • Configurable Sequences Between the SLEEP and ACTIVE States (OTP Programmable)
    • One Dedicated Digital Output Signal (REGEN) that can be Included in the Start-Up Sequence
    • Three Digital Output Signals MUXed With GPIO that can be Included in the Start-Up Sequence
    • Selectable Control Interface
      • One Serial Peripheral Interface (SPI) for Resource Configurations and DVS Control
      • Two I2C Interfaces. One Dedicated for DVS Control, and a General Purpose I2C Interface for Resource Configuration and DVS Control
  • Undervoltage Lockout
  • System Voltage Range from 3.135 to 5.25 V
  • Package Options
    • 12-mm × 12-mm 169-pin nFBGA with 0,8-mm Pin Pitch
  • Seven Step-Down Switched-Mode Power Supply (SMPS) Regulators:
    • One 0.7 to 1.65 V at 6 A (10-mV Steps)
      • Dual-Phase Configuration With Digital Voltage Scaling (DVS) Control
    • One 0.7 to 1.65 V at 4 A (10-mV Steps)
      • Dual-Phase Configuration With DVS Control
    • One 0.7 to 3.3 V at 3 A (10 or 20-mV Steps)
      • Single-Phase Configuration
      • This Regulator can be Combined With the 6 A Resulting in a 9-A Triple-Phase Regulator (DVS Controlled)
    • Two 0.7 to 3.3 V at 2 A (10 or 20-mV Steps)
      • Single-Phase Configuration
      • One Regulator With DVS Control That can also be Configured as a 3-A Regulator
    • Two 0.7 to 3.3 V at 1 A (10 or 20-mV Steps)
      • Single-Phase Configuration
      • One Regulator With DVS Control
    • Output Current Measurement in All Except 1-A SMPS Regulators
    • Differential Remote Sensing (Output and Ground) in Dual-Phase and Triple-Phase Regulators
    • Hardware and Software-Controlled Eco-mode™ up to 5 mA with 15-µA Quiescent Current
    • Short-Circuit Protection
    • Powergood Indication (Voltage and Overcurrent Indication)
    • Internal Soft-Start for In-Rush Current Limitation
    • Ability to synchronize SMPS to External Clock or Internal Fallback Clock With Phase Synchronization
  • Seven General-Purpose Low Dropout Regulators (LDOs) with 50-mV Steps:
    • Two 0.9 to 3.3-V LDOs at 300 mA With Preregulated Supply
    • Two 0.9 to 3.3-V LDOs at 200 mA With Preregulated Supply
    • One 0.9 to 3.3-V LDOs at 50 mA With Preregulated Supply
    • One 100-mA USB LDO
    • One 0.9 to 3.3-V, Low-Noise LDO up to 100 mA (Low-Noise Performance up to 50 mA)
    • Two Additional LDOs for PMU Internal Use
    • Short-Circuit Protection
  • Clock Management 16-MHz Crystal Oscillator and 32-kHz RC Oscillator
    • One Buffered 32-kHz Output
  • Real-Time Clock (RTC) With Alarm Wake-Up Mechanism
  • 12-bit Sigma-Delta General-Purpose Analog-to-Digital-Converter (GPADC) With Three External Input Channels and Six Internal Channels for Self Monitoring
  • Thermal Monitoring
    • High Temperature Warning
    • Thermal Shutdown
  • Control
    • Configurable Power-Up and Power-Down Sequences (One-Time Programmable [OTP])
    • Configurable Sequences Between the SLEEP and ACTIVE States (OTP Programmable)
    • One Dedicated Digital Output Signal (REGEN) that can be Included in the Start-Up Sequence
    • Three Digital Output Signals MUXed With GPIO that can be Included in the Start-Up Sequence
    • Selectable Control Interface
      • One Serial Peripheral Interface (SPI) for Resource Configurations and DVS Control
      • Two I2C Interfaces. One Dedicated for DVS Control, and a General Purpose I2C Interface for Resource Configuration and DVS Control
  • Undervoltage Lockout
  • System Voltage Range from 3.135 to 5.25 V
  • Package Options
    • 12-mm × 12-mm 169-pin nFBGA with 0,8-mm Pin Pitch

The TPS659037 device is an integrated power-management IC (PMIC). The device provides seven configurable step-down converters with up to 6 A of output current for memory, processor core, input-output (I/O), or preregulation of LDOs. One of these configurable step-down converters can be combined with another 3-A regulator to allow up to 9 A of output current. All of the step-down converters can synchronize to an external clock source between 1.7 MHz and 2.7 MHz, or an internal fallback clock at 2.2 MHz.

The TPS659037 device contains seven LDO regulators for external use. These LDO regulators can be supplied from either a system supply or a preregulated supply. The power-up and power-down controller is configurable and supports any power-up and power-down sequences (OTP based). The TPS659037 device includes a 32-kHz RC oscillator to sequence all resources during power up and power down. In cases where a fast start up is needed, a 16-MHz crystal oscillator is also included to quickly generate a stable 32-kHz for the system. All LDOs and SMPS converters can be controlled by the SPI or I2C interface, or by power request signals. In addition, voltage scaling registers allow transitioning the SMPS to different voltages by SPI, I2C, or roof and floor control.

One dedicated pin in each package can be configured as part of the power-up sequence to control external resources. General-purpose input-output (GPIO) functionality is available and two GPIOs can be configured as part of the power-up sequence to control external resources. Power request signals enable power mode control for power optimization. The device includes a general-purpose sigma-delta analog-to-digital converter (GPADC) with three external input channels.

The TPS659037 device is available in a 13-pin × 13-pin nFBGA package with a 0,8-mm pitch.

The TPS659037 device is an integrated power-management IC (PMIC). The device provides seven configurable step-down converters with up to 6 A of output current for memory, processor core, input-output (I/O), or preregulation of LDOs. One of these configurable step-down converters can be combined with another 3-A regulator to allow up to 9 A of output current. All of the step-down converters can synchronize to an external clock source between 1.7 MHz and 2.7 MHz, or an internal fallback clock at 2.2 MHz.

The TPS659037 device contains seven LDO regulators for external use. These LDO regulators can be supplied from either a system supply or a preregulated supply. The power-up and power-down controller is configurable and supports any power-up and power-down sequences (OTP based). The TPS659037 device includes a 32-kHz RC oscillator to sequence all resources during power up and power down. In cases where a fast start up is needed, a 16-MHz crystal oscillator is also included to quickly generate a stable 32-kHz for the system. All LDOs and SMPS converters can be controlled by the SPI or I2C interface, or by power request signals. In addition, voltage scaling registers allow transitioning the SMPS to different voltages by SPI, I2C, or roof and floor control.

One dedicated pin in each package can be configured as part of the power-up sequence to control external resources. General-purpose input-output (GPIO) functionality is available and two GPIOs can be configured as part of the power-up sequence to control external resources. Power request signals enable power mode control for power optimization. The device includes a general-purpose sigma-delta analog-to-digital converter (GPADC) with three external input channels.

The TPS659037 device is available in a 13-pin × 13-pin nFBGA package with a 0,8-mm pitch.
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Technical documentation

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Type Title Date
* Data sheet TPS659037 Power management unit (PMU) for processor datasheet (Rev. G) PDF | HTML 20 Aug 2018
* User guide TPS659037 Register Map (Rev. B) 12 Feb 2019
Application note TPS659037 Design Checklist (Rev. B) 09 Jun 2022
Application note POR Generation in TPS65903x, TPS65917-Q1, TPS65919-Q1, and TPS65916 Devices (Rev. A) 21 Sep 2018
User guide TPS659037 user's guide to power AM574x, AM572x, and AM571x (Rev. F) 16 Mar 2018
Application note Guide to Using the GPADC in TPS65903x, TPS65917-Q1, TPS65919-Q1, and TPS65916 de (Rev. A) 13 Dec 2017
Technical article How to implement remote sense in your PMIC PDF | HTML 17 Nov 2016
Technical article Using PMICs to support a wide range of power sequencing requirements PDF | HTML 01 Nov 2016
Technical article Using TPS659037 to power the Sitara AM57x processors PDF | HTML 16 Feb 2016
EVM User's guide TPS659037EVM User's Guide 03 Nov 2015
Application note TPS659037 Design Guide 21 Sep 2015

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

TPS659037EVM-090 — TPS659037 Power Management IC Evaluation Module

The TPS659037 device is an integrated power-management integrated circuit (PMIC) for industrial and consumer applications.  The device provides seven configurable step-down converters with up to 6A of output current for memory, processor core, input/output (I/O), or pre-regulation of LDOs. (...)

User guide: PDF
Not available on TI.com
Evaluation board

BEAGLE-3P-BBONE-AI — BeagleBone® AI AM5729 development board for embedded Artificial Intelligence

What is BeagleBone® AI?

Built on the proven BeagleBoard.org® open source Linux approach, BeagleBone® AI fills the gap between small SBCs and more powerful industrial computers. Based on the Texas Instruments, Sitara™ AM5729 processor, developers have access to a highly integrated and (...)

From: BeagleBoard.org Foundation
User guide: PDF
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Simulation model

TPS659037 Unencrypted PSpice Transient Model Package (Rev. A)

SLIM334A.ZIP (591 KB) - PSpice Model
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Reference designs

TIDEP0076 — 3D Machine Vision Reference Design Based on AM572x Processor with DLP® Structured Light

The TIDEP0076 3D machine vision design describes an embedded 3D scanner based on the structured light principle. A digital camera along with a Sitara™ AM57xx processor System on Chip (SoC)  is used to capture reflected light patterns from a DLP4500-based projector. Subsquent processing (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDEP0079 — EtherCAT® Reference Design on Sitara AM57x Gb Ethernet and PRU-ICSS with Time Triggered Send

The TIDEP0079 reference design demonstrates an EtherCAT® master interface running on the Sitara™ AM572x processor using the EC-Master stack from acontis. This EtherCAT master solution can be used for EtherCAT-based PLC or motion control applications. EtherCAT master is profiled on both (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-010010 — Industrial gigabit Ethernet PHY reference design

PLC applications require high speed gigabit Ethernet interface. This can be realized using our reference design which implements the DP83867IR industrial gigabit Ethernet physical layer transceiver to the gigabit Ethernet MAC peripheral block inside the Sitara™ AM5728 processor.
Design guide: PDF
Schematic: PDF
Reference designs

TIDEP-0075 — Industrial Communications Gateway PROFINET IRT to PROFIBUS Master Reference Design

PROFINET is becoming the leading industrial Ethernet protocol in automation due to its high-speed, deterministic communications and enterprise connectivity. However, as the world’s most popular fieldbus, PROFIBUS’s importance and usage will continue for many years due to legacy (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDEP0074 — Packet Processing Engine Reference Design for IEC61850 GOOSE Forwarding

The TIDEP0074 reference design demonstrates packet switching and filtering logic implemented in the M4 core of AM572x based upon the Ethertype, MAC address and Application ID (APPID) of GOOSE packets received from the PRU-ICSS. Packets are filtered and routed to destinations in order to allow (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDEP0078 — OPC UA Data Access Server for AM572x Reference Design

OPC UA is an industrial machine-to-machine protocol designed to allow interoperability and communication between all machines connected under Industry 4.0. This reference design demonstrates use of the Matrikon OPC™ OPC UA server development kit (SDK) to allow communications using an OPC UA (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDEP0046 — Monte-Carlo Simulation on AM57x Using OpenCL for DSP Acceleration Reference Design

TI’s high performance ARM® Cortex®-A15 based AM57x processors also integrate C66x DSPs. These DSPs were designed to handle high signal and data processing tasks that are often required by industrial, automotive and financial applications. The AM57x OpenCL implementation makes it easy (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDEP0047 — Power and Thermal Design Considerations Using TI's AM57x Processor Reference Design

This is a reference design based on the AM57x processor and companion TPS659037 power management integrated circuit (PMIC).  This design specifically highlights important power and thermal design considerations and techniques for systems designed with AM57x and TPS659037.  It includes (...)
Design guide: PDF
Schematic: PDF
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NFBGA (ZWS) 169 Ultra Librarian
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