TLK105L is not recommended for new designs.
This product continues to be in production to support existing customers. Please consider one of these alternatives:
Similar but not functionally equivalent to the compared device:
DP83822IF ACTIVE Low-power, robust 10/100-Mbps Ethernet PHY transceiver with fiber support & 16-kV ESD The DP83822IF device is a pin-compatible upgrade of the TLK105 with fiber support.

Product details


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  • Low-Power Consumption:
    • Single Supply: <205 mW PHY, 275 mW With Center Tap (Typical)
    • Dual Supplies: <126 mW PHY, 200 mW With Center Tap (Typical)
  • Programmable Power Back Off to Reduce PHY Power up to 20% in Systems With Shorter Cables
  • IEEE 1588 SFD Indication Enables Time Stamping by a Controller or Processor
  • Low Deterministic Latency Supports IEEE1588 Implementation
  • Cable Diagnostics
  • Programmable Fast Link Down Modes, <10 µs Reaction Time
  • Variable I/O voltage range: 3.3V, 2.5V, 1.8V
  • MAC Interface I/O voltage range:
    • MII I/O voltage range: 3.3V, 2.5V, 1.8V
    • RMII I/O voltage range: 3.3V, 2.5V
  • Fixed TX Clock to XI, With Programmable Phase Shift
  • Auto-MDIX for 10/100Mbs
  • Energy Detection Mode
  • MII and RMII Capabilities
  • IEEE 802.3u MII
  • Error-Free 100Base-T Operation up to 150 Meters Under Typical Conditions
  • Error-Free 10Base-T Operation up to 300 Meters Under Typical Conditions
  • Serial Management Interface
  • IEEE 802.3u Auto-Negotiation and Parallel Detection
  • IEEE 802.3u ENDEC, 10Base-T Transceivers and Filters
  • IEEE 802.3u PCS, 100Base-TX Transceivers
  • Integrated ANSI X3.263 Compliant TP-PMD Physical Sublayer with Adaptive Equalization and Baseline Wander Compensation
  • Programmable LED Support Link, Activity
  • 10/100Mbs Packet BIST (Built in Self Test)
  • HBM ESD Protection on RD± and TD± of 16 kV
  • 32-pin VQFN (5 mm) × (5 mm)

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The TLK10xL is a single-port Ethernet PHY for 10Base-T and 100Base TX signaling, integrating all the physical-layer functions needed to transmit and receive data on standard twisted-pair cables. The device supports the standard Media Independent Interface (MII) and Reduced Media Independent Interface (RMII) for direct connection to a Media Access Controller (MAC).

The device is designed for power-supply flexibility, and can operate with a single 3.3-V power supply or with combinations of 3.3-V and 1.55-V power supplies for reduced power operation.

The TLK10xL uses mixed-signal processing to perform equalization, data recovery, and error correction to achieve robust operation over CAT 5 twisted-pair wiring. The TLK10xL not only meets the requirements of IEEE 802.3, but maintains high margins in terms of cross-talk and alien noise.

The TLK10xL Ethernet PHY has a special Power Back Off mode to conserve power in systems with relatively short cables. This mode provides the flexibility to reduce system power when the system is not required to drive the standard IEEE 802.3 100-m cable length, or the extended 150m, error-free cable reach of the TLK10xL. For more detail, see application note SLLA328.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 6
Type Title Date
* Datasheet TLK10xL Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer Transceiver datasheet (Rev. D) Apr. 27, 2016
Application note Selection and specification of crystals for Texas Instruments ethernet physical Feb. 06, 2019
User guide TLK10xL EVM User Guide Jul. 02, 2014
User guide TLK1xx Software GUI Aug. 15, 2013
User guide TLK105/6L EVM Aug. 12, 2013
Application note TLK1XX Design & Layout Guide (Rev. A) Aug. 15, 2012

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Software development

SLLC438.ZIP (7062 KB)
Ethernet PHY Linux drivers & tools
ETHERNET-SW The Linux drivers for Texas Instruments' Ethernet physical layer (PHY) transceivers support communication through the serial management interface (MDC/MDIO) to configure and read PHY registers.

The USB-2-MDIO software lets you directly access the registers during debug and prototyping.  (...)

SLLC439.ZIP (27327 KB)

Design tools & simulation

PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide

Reference designs

Industrial Communications Gateway PROFINET IRT to PROFIBUS Master Reference Design
TIDEP-0075 — PROFINET is becoming the leading industrial Ethernet protocol in automation due to its high-speed, deterministic communications and enterprise connectivity. However, as the world’s most popular fieldbus, PROFIBUS’s importance and usage will continue for many years due to legacy (...)
document-generic Schematic document-generic User guide
Packet Processing Engine Reference Design for IEC61850 GOOSE Forwarding
TIDEP0074 The TIDEP0074 reference design demonstrates packet switching and filtering logic implemented in the M4 core of AM572x based upon the Ethertype, MAC address and Application ID (APPID) of GOOSE packets received from the PRU-ICSS. Packets are filtered and routed to destinations in order to allow (...)
document-generic Schematic document-generic User guide
OPC UA Data Access Server for AM572x Reference Design
TIDEP0078 — OPC UA is an industrial machine-to-machine protocol designed to allow interoperability and communication between all machines connected under Industry 4.0. The TIDEP0078 TI Design demonstrates use of the MatrikonOPC™ OPC UA server development kit (SDK) to allow communications using an OPC UA (...)
document-generic Schematic document-generic User guide
EtherCAT® Reference Design on Sitara AM57x Gb Ethernet and PRU-ICSS with Time Triggered Send
TIDEP0079 The TIDEP0079 reference design demonstrates an EtherCAT® master interface running on the Sitara™ AM572x processor using the EC-Master stack from acontis. This EtherCAT master solution can be used for EtherCAT-based PLC or motion control applications. EtherCAT master is profiled on both the (...)
document-generic Schematic document-generic User guide
Single Chip Drive for Industrial Communications and Motor Control
TIDEP0025 This TI design implements a hardware interface solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The platform also allows designers to implement real-time EtherCAT communications standards in a broad range of industrial automation equipment. It enables designers (...)
document-generic Schematic document-generic User guide
Sercos III Slave For AM437x Communication Development Platform Reference Design
TIDEP0039 The TIDEP0039 Sercos III Slave For AM437x Communication Development Platform Reference Design combines the AM437x Sitara processor family from Texas Instruments (TI) and the Sercos III media access control (MAC) layer into a single system-on-chip (SoC) solution. Targeted for Sercos III slave (...)
document-generic Schematic document-generic User guide
ARM MPU with Integrated HIPERFACE DSL Master Interface Reference Design
TIDEP0035 Implementation of HIPERFACE DSL Master protocol on Industrial Communication Sub-System (PRU-ICSS). The two wire interface allows for integration of position feedback wires into motor cable.  Complete solution consists of AM437x PRU-ICSS firmware and TIDA-00177 transceiver reference design.
document-generic Schematic document-generic User guide
EnDat 2.2 System Reference Design
TIDEP0050 The TIDEP0050 TI Design implements the EnDat 2.2 Master protocol stack and hardware interface solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The design is composed of the EnDat 2.2 Master protocol stack, half-duplex communications using RS485 transceivers and (...)
document-generic Schematic document-generic User guide
Real-time Ethernet Tracer with PRU-ICSS Reference Design
TIDEP0064 — Real-time ethernet and industrial ethernet are used in the factory automation floor to control automated production. Monitoring the ethernet traffic in such areas is an essential maintains and error analysis tool.  The TIDEP0064 reference design is a real-time ethernet tracer implementation for (...)
document-generic Schematic document-generic User guide

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