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Sink and Source DDR Termination Regulator

TPS51200A-Q1

ACTIVE

Product details

Parameters

DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3 Control mode D-CAP, S3, S4/S5 Iout VTT (Max) (A) 3 Iq (Typ) (mA) 0.5 Output VREF, VTT Vin (Min) (V) 1.1 Vin (Max) (V) 3.5 Features S3/S5 Support Rating Automotive Operating temperature range (C) -40 to 125 open-in-new Find other DDR memory power ICs

Package | Pins | Size

VSON (DRC) 10 9 mm² 3 x 3 open-in-new Find other DDR memory power ICs

Features

  • AEC-Q100 Qualified for Automotive Applications:
    • Device Temperature Grade 1:
      –40°C ≤ TA ≤ 125°C
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C4B
  • Extended Reliability Testing
  • Input Voltage: Supports 2.5-V Rail and 3.3-V Rail
  • VLDOIN Voltage Range: 1.1 V to 3.5 V
  • Sink and Source Termination Regulator Includes Droop Compensation
  • Requires Minimum Output Capacitance of 20-µF (typically 3 × 10-µF MLCCs) for Memory Termination Applications (DDR)
  • PGOOD to Monitor Output Regulation
  • EN Input
  • REFIN Input Allows for Flexible Input Tracking Either Directly or Through Resistor Divider
  • Remote Sensing (VOSNS)
  • ±10-mA Buffered Reference (REFOUT)
  • Built-in Soft-Start, UVLO and OCL
  • Thermal Shutdown
  • Meets DDR, DDR2 JEDEC Specifications; Supports DDR3 and Low-Power DDR3 and DDR4 VTT Applications
  • VSON-10 Package With Exposed Thermal Pad

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Description

The TPS51200A-Q1 device is a sink and source double-data-rate (DDR) termination regulator specifically designed for low input voltage, low-cost, low-noise systems where space is a key consideration.

The device maintains a fast transient response and only requires a minimum output capacitance of 20 µF. The device supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, and Low Power DDR3 and DDR4 VTT bus termination.

In addition, the device provides an open-drain PGOOD signal to monitor the output regulation and an EN signal that can be used to discharge VTT during S3 (suspend to RAM) for DDR applications.

The device is available in the thermally-efficient VSON-10 package, and is rated both green and Pb-free. The device is specified from –40°C to 125°C.

open-in-new Find other DDR memory power ICs
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Technical documentation

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No results found. Please clear your search and try again. View all 6
Type Title Date
* Datasheet TPS51200A-Q1 Sink and Source DDR Termination Regulator datasheet (Rev. A) Dec. 13, 2018
Application notes DDR VTT Power Solutions: A Competitive Analysis Apr. 27, 2018
Technical articles A New Understanding: Blast Motion redefines movement, tracking and training for athletes. Aug. 06, 2014
Technical articles Improving Fly-Buck Regulation Using Opto (Part-1) Jul. 15, 2014
Technical articles Altium and WEBENCH – together at last Jul. 12, 2014
Technical articles Using telemetry in point-of-load applications Jun. 24, 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$49.00
Description

The TPS51200EVM evaluation board, HPA322A is designed to evaluate the performance and characteristics of TI's cost optimized DDR/DDR2/DDR3/LP DDR3 VTT termination regulator, the TPS51200. The TPS51200 is designed to provide proper termination voltage and a 10-mA buffered reference voltage for DDR (...)

Features
  • Input Voltage: Support 2.5V Rail and 3.3V Rail
  • VLDOIN, VDDQ Voltage Range: 1.2V-2.5V
  • Build-in transient load switches (with both sinking and sourcing capability) to emulate the sink/source transient behavior which helps to evaluate the dynamic performance. For ease of use, both load step and timing of (...)

Reference designs

REFERENCE DESIGNS Download
Automotive multi-rail power supply for driving monitoring system reference design
PMP30785 — This reference design shows the performance of a non-isolated automotive power supply for a driving monitoring system for the electronic control unit (ECU). The reference design includes our power portfolio with nine power sockets.
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Cascade imaging radar capture reference design using Jacinto™ ADAS processor
TIDEP-01017 The cascade development kit has two main use cases:
  1. To use the MMWCAS-DSP-EVM as a capture card to fully evaluate the AWR2243 four-chip cascade performance by using the mmWave studio tool, please read the TIDEP-01012 design guide.
  2. To use the MMWCAS-DSP-EVM to develop radar real time SW application (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
VSON (DRC) 10 View options

Ordering & quality

Support & training

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