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TPS51200A-Q1 ACTIVE Sink and Source DDR Termination Regulator This product has added features for increased robustness.

Product details

DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3 Control mode D-CAP, S3, S4/S5 Iout VTT (Max) (A) 3 Iq (Typ) (mA) 0.5 Output VREF, VTT Vin (Min) (V) 1.1 Vin (Max) (V) 3.5 Features S3/S5 Support Rating Automotive Operating temperature range (C) -40 to 125
DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3 Control mode D-CAP, S3, S4/S5 Iout VTT (Max) (A) 3 Iq (Typ) (mA) 0.5 Output VREF, VTT Vin (Min) (V) 1.1 Vin (Max) (V) 3.5 Features S3/S5 Support Rating Automotive Operating temperature range (C) -40 to 125
VSON (DRC) 10 9 mm² 3 x 3 VSON (DRC) 10 9 mm² 3.00 x 3.00
  • Qualified for Automotive Applications
  • AEC-Q100 Test Guidance With the Following Results:
    • Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C4B
  • Input Voltage: Supports 2.5-V Rail and 3.3-V Rail
  • VLDOIN Voltage Range: 1.1 V to 3.5 V
  • Sink/Source Termination Regulator Includes Droop Compensation
  • Requires Minimum Output Capacitance of 20-µF (typically 3 × 10-µF MLCCs) for Memory Termination Applications (DDR)
  • PGOOD to Monitor Output Regulation
  • EN Input
  • REFIN Input Allows for Flexible Input Tracking Either Directly or Through Resistor Divider
  • Remote Sensing (VOSNS)
  • ±10-mA Buffered Reference (REFOUT)
  • Built-in Soft Start, UVLO and OCL
  • Thermal Shutdown
  • Meets DDR, DDR2 JEDEC Specifications; Supports DDR3, DDR3L, Low-Power DDR3 and DDR4 VTT Applications
  • VSON-10 Package With Exposed Thermal Pad
  • Qualified for Automotive Applications
  • AEC-Q100 Test Guidance With the Following Results:
    • Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C4B
  • Input Voltage: Supports 2.5-V Rail and 3.3-V Rail
  • VLDOIN Voltage Range: 1.1 V to 3.5 V
  • Sink/Source Termination Regulator Includes Droop Compensation
  • Requires Minimum Output Capacitance of 20-µF (typically 3 × 10-µF MLCCs) for Memory Termination Applications (DDR)
  • PGOOD to Monitor Output Regulation
  • EN Input
  • REFIN Input Allows for Flexible Input Tracking Either Directly or Through Resistor Divider
  • Remote Sensing (VOSNS)
  • ±10-mA Buffered Reference (REFOUT)
  • Built-in Soft Start, UVLO and OCL
  • Thermal Shutdown
  • Meets DDR, DDR2 JEDEC Specifications; Supports DDR3, DDR3L, Low-Power DDR3 and DDR4 VTT Applications
  • VSON-10 Package With Exposed Thermal Pad

The TPS51200-Q1 device is a sink and source double-data-rate (DDR) termination regulator specifically designed for low input voltage, low-cost, low-noise systems where space is a key consideration.

The TPS51200-Q1 device maintains a fast transient response and only requires a minimum output capacitance of 20 µF. The TPS51200-Q1 device supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, DDR3L, Low Power DDR3 and DDR4 VTT bus termination.

In addition, the TPS51200-Q1 device provides an open-drain PGOOD signal to monitor the output regulation and an EN signal that can be used to discharge VTT during S3 (suspend to RAM) for DDR applications.

The TPS51200-Q1 device is available in the thermally-efficient VSON-10 package, and is rated both green and Pb-free. The device is specified from –40°C to 125°C.

The TPS51200-Q1 device is a sink and source double-data-rate (DDR) termination regulator specifically designed for low input voltage, low-cost, low-noise systems where space is a key consideration.

The TPS51200-Q1 device maintains a fast transient response and only requires a minimum output capacitance of 20 µF. The TPS51200-Q1 device supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, DDR3L, Low Power DDR3 and DDR4 VTT bus termination.

In addition, the TPS51200-Q1 device provides an open-drain PGOOD signal to monitor the output regulation and an EN signal that can be used to discharge VTT during S3 (suspend to RAM) for DDR applications.

The TPS51200-Q1 device is available in the thermally-efficient VSON-10 package, and is rated both green and Pb-free. The device is specified from –40°C to 125°C.

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Technical documentation

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Type Title Date
* Data sheet TPS51200-Q1 Sink and Source DDR Termination Regulator datasheet (Rev. C) 25 Jul 2016
Application note DDR VTT Power Solutions: A Competitive Analysis (Rev. A) 09 Jul 2020
Technical article Improving DDR memory performance in automotive applications 22 Jun 2017
Application note Pwr Ref Design f/'C6472 12-Vin Digital Pwr Controllers and LDOs 28 Apr 2010
Application note Power Two Xilinx(TM) LX240 Virtex-6(TM) Devices 20 Apr 2010
Application note Power Ref Design for TMS320C6472 5Vin DC/DC Converters (1x C6472) 31 Mar 2010
Application note 'C6472 12Vin Flexible Pwr Design Using DCDC Controllers and LDOs (8x C6472) 26 Mar 2010
Application note Power Reference Design for the 'C6472, 12V DCDC Controllers, and LDOs 26 Mar 2010
Application note TMS320C6472 5V Input Pwr Design, Integrated FET DC/DC Converters and Controllers 26 Mar 2010

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

TPS51200EVM — TPS51200 Sink Source DDR Termination Regulator

The TPS51200EVM evaluation board, HPA322A is designed to evaluate the performance andcharacteristics of TI's cost optimized DDR/DDR2/DDR3/LP DDR3 VTT termination regulator, the TPS51200. The TPS51200 is designed to provide proper termination voltage and a 10-mA buffered reference voltage for DDR (...)

Simulation model

TPS51200 TINA-TI Start-Up Transient Reference Design

SLUM148.TSC (127 KB) - TINA-TI Reference Design
Simulation model

TPS51200 TINA-TI Transient Spice Model

SLUM149.ZIP (18 KB) - TINA-TI Spice Model
Simulation model

TPS51200 TINA-TI Average Reference Design

SLUM150.TSC (755 KB) - TINA-TI Reference Design
Simulation model

TPS51200 TINA-TI Average Spice Model

SLUM151.ZIP (17 KB) - TINA-TI Spice Model
Simulation model

TPS51200 PSpice Transient Model (Rev. A)

SLVM068A.ZIP (38 KB) - PSpice Model
Simulation model

TPS51200 PSpice Average Model

SLVM069.ZIP (30 KB) - PSpice Model
Reference designs

TIDA-00805 — Automotive Off-Battery Processor Power Reference Design for ADAS and Infotainment

The TIDA-00805 reference design is an off-battery automotive power solution targeting processors in advanced driver assistance systems (ADAS) like surround view, front camera and driver monitoring, as well as infotainment systems such as cluster and head unit. The design operates directly from a (...)
Reference designs

TIDA-080004 — Electronics and LED Driver Reference Design for Augmented Reality Head-Up Displays

This reference design provides an electronics subsystem designed to drive an automotive augmented reality (AR) head-up display (HUD). DLP® technology enables bright, crisp, highly saturated head-up displays that project critical driving information onto the windshield of the car, reducing (...)
Reference designs

TIDA-01425 — Automotive Stand-Alone Gateway Reference Design with Ethernet and CAN

The TIDA-01425 is a subsystem reference design for automotive gateways focused on increasing bandwidth and processing power in gateway applications. The design implements Ethernet physical layer transceivers (PHYs) for increased bandwidth along with an automotive processor for greater processing (...)
Reference designs

TIDA-00801 — Automotive Off-Battery Infotainment Processor Power Reference Design

The TIDA-00801 reference design is a full off-battery to point of load power solution supporting input voltages as low as 2V.  It uses the Boost plus Buck DC/DC regulator TPS43330A-Q1 supporting an  input voltage range of  2V to 40V and allowing the design to support not only (...)
Reference designs

TIDA-00346 — Cost-optimized power supply solution for entry-level core application processor-based ADAS systems

The TIDA-00346 design provides the power supply rails necessary for typical  entry-level application processors in automotive advanced driver assistance systems (ADAS) applications.  The design uses several individual DC/DC voltage regulators as well as load switches and linear regulators (...)
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VSON (DRC) 10 View options

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