JESD204 technology
Take advantage of an encoded SerDes for optimal synchronization, clock recovery and DC balance with our JESD-compliant products and designs
What is JESD204?
JESD204 technology is a standardized serial interface between data converters (ADCs and DACs) and logic devices (FPGAs or ASICs) which uses encoding for SerDes synchronization, clock recovery and DC balance. Our JESD-compliant products and designs help you significantly improve the performance of high-density systems across a variety of JESD204B and JESD204C application areas.
Why choose TI for your JESD204 system?
Achieve lower system cost
Access free of charge, our JESD204 rapid design IP for use with our high-speed data converters including support from our JESD204 experts.
Flexible and easy to use
Start using fewer FPGA resources, with pre-configurable and optimizable firmware specifically for your FPGA platform, data converter and JESD204 mode.
Accelerate design time
Reduce your design cycle time with support from our knowledgable engineers, to help you to configure the IP for your exact mode.
Our free firmware expedites development time
JESD204 快速設計 IP，適用連接到 TI 高速資料轉換器的 FPGA
JESD204 快速設計 IP 被設計用於幫助 FPGA 工程師快速實現可運作的 JESD204 系統，從而加速開發過程。該 IP 的架構設計使得下游數位處理和其他應用邏輯能夠隔離於 JESD204 通訊協定的大多數性能和時序關鍵約束之外。該 IP 能夠幫助設計人員減少韌體開發時間並簡化 FPGA 的整合。
JESD204 快速設計 IP 無需權利金，用於 TI 高速資料轉換器。TI 將協助使用者配置初始連結，針對特定 FPGA 平台與 TI 資料轉換器 JMODE 之間的使用進行自訂。TI 將在 IP 測試完成並準備部署後，透過安全下載連結提供 IP。
JESD204 快速設計 IP 支援下列 (...)
Design and development resources for JESD204
高速資料轉換器 pro 軟體
這款高速資料轉換器專業 GUI 是一款 PC（與 Windows® XP/7/10 相容）程式，旨在協助評估大多數 TI 高速資料轉換器 [類比轉數位轉換器 (ADC) 和數位轉類比轉換器 (DAC)] 和類比前端 (AFE) 平台。DATACONVERTERPRO-SW 旨在支援整個 TSW14xxx 系列資料擷取和模式產生卡，為時域和頻域中的資料轉換器分析提供強大且快速的解決方案，並支援單音、多音和調變訊號。此 GUI 也與 TI 模式產生 GUI 相容，可快速合成單音、多音和調變訊號。
使用者可以向 DATACONVERTERPRO-SW 提供自訂模式，以載入到 TI DAC。支援從 (...)
適用於 12 位元數位器的可擴充 20.8 GSPS 參考設計
適用於 DSO、雷達和 5G 無線測試儀的多通道 JESD204B 15 GHz 時鐘參考設計
適用於雷達應用的多通道 RF 收發器參考設計
此參考設計為 8 通道類比前端 (AFE)，採用兩個 AFE7444 4 通道 RF 收發器和 LMK04828-LMX2594 架構時脈子系統，可讓設計擴充至 16 通道或更多通道。每個 AFE 通道包含一個 14 位元、9GSPS DAC 和一個 3GSPS ADC，同步化至低於 10ps 的偏斜，於 2.6GHz 時之動態範圍大於 75-dB。
技術資源
Adaptive Drive Angle Adjust
Ready to make the jump to JESD204B? White Paper (Rev. B)
System Design Considerations when Upgrading from JESD204B to JESD204C (Rev. A)
Support and training for JESD204
Visit our E2E™ design support forum
Our E2E™ design support forums are an engineer’s go-to source for help throughout every step of the design process. Connect with our engineers or browse through JESD204 related posts to help you quickly solve your design challenges.
JESD204B video series
Watch our JESD204B video series which explores the basic concepts related to the JESD204B SerDes standard in relation to high-speed data converter products.
Explore JESD204-compliant products by category
Clock jitter cleaners & synchronizers
Enable precise clock jitter performance with our portfolio of low-power network synchronizers and lowest jitter, JESD204B-compliant jitter cleaners.
High-speed JESD204 interface ADCs
Discover our high-speed analog-to-digital converter (ADC) products that use the JEDEC SERDES standard JESD204 to output high speed data.
High-speed JESD204 interface DACs
Explore our high-speed digital-to-analog converter (DAC) products that use the JEDEC SERDES standard JESD204 to input high speed data.
RF PLLs & synthesizers
Achieve ultra-low phase noise for high-performance test instrumentation, satellites, radar and 5G wireless systems.