Taktgeber & Timing

Takt-Jitter-Cleaner & Synchronisierer – Design & development

Featured evaluation modules

LMK04610EVM

Evaluation module for our ultra-low noise and low-power JESD204B-compliant dual-loop jitter cleaner

LMK04828BEVM

Evaluation module for our ultra-low jitter synthesizer and jitter cleaner

LMK04906BEVAL

Evaluation module for our low-noise clock jitter cleaner and multiplier with 6 programmable outputs

LMK04816BEVAL

Evaluation module for our 3-input low-noise clock jitter cleaner with dual-loop PLLs

LMK04808BEVAL

Evaluation module for our low-noise clock jitter cleaner with dual-loop PLLs and integrated VCO

Featured reference designs

RF-sampling 4-GSPS ADC reference design with 8-GHz DC-coupled differential amplifier

Synchronization of JESD204B giga-sample ADCs using the Xilinx platform for phased array radar systems

Clocking solution reference design for GSPS ADCs

50-Ω 2-GHz oscilloscope front-end reference design

6AK2L06 DSP+ARM processor with JESD204B attach to wideband ADCs and DACs

Featured tools and software

Clock Architect

This online design tool helps you find the right clock for your system by generating complete clock-tree solutions. The tool generates multiple solutions that optimized for performance, cost or board space.

Texas Instruments clocks & synthesizers (TICS) pro software

Use our TICSPRO-SW software to program the evaluation modules (EVMs) for our PLLs and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.

Clock design tool

Our offline clock design tool helps you with device selection and designing configurations and simulations including loop filter designs.