SLUSDQ4 April 2019 BQ79606A-Q1
The decimation ratio (DR) directly correlates to how quickly a conversion result is available to be read from the ADC. Lower DR corresponds to faster conversion time and lower effective number of bits (ENOB).
The reference voltage used in the modulator has an internal correction that is applied automatically. This correction is shown in Figure 4 as occurring immediately after the SINC3 filter. This correction becomes overhead to the conversion time. The uncorrected value is also made available for host access in the event that external correction is required to account for reference voltage shifts. See Table 1 for details about the conversion times and ENOB at different DRs.
The decimation ratio is configured using the CELL_ADC_CONF1[DR] (for the cell ADCs) and AUX_ADC_CONF[DR] (for the AUX ADC). The temperature ADC settings match the CELL ADC settings.
|ADCCONF0[DR]||Decimation Ratio||ADC Conversion Time (Typical) [µs]||ENOB|