SLVSGV9 august   2023 DRV8213

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Diagrams
    7. 7.7 Typical Operating Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 External Components
    4. 8.4 Feature Description
      1. 8.4.1 Bridge Control
      2. 8.4.2 Current Sense and Regulation (IPROPI)
        1. 8.4.2.1 Current Sensing and Current Mirror Gain Selection
        2. 8.4.2.2 Current Regulation
      3. 8.4.3 Hardware Stall Detection
      4. 8.4.4 Protection Circuits
        1. 8.4.4.1 Overcurrent Protection (OCP)
        2. 8.4.4.2 Thermal Shutdown (TSD)
        3. 8.4.4.3 VM Undervoltage Lockout (UVLO)
    5. 8.5 Device Functional Modes
      1. 8.5.1 Active Mode
      2. 8.5.2 Low-Power Sleep Mode
      3. 8.5.3 Fault Mode
    6. 8.6 Pin Diagrams
      1. 8.6.1 Logic-Level Inputs
      2. 8.6.2 Tri-Level Input
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Brushed DC Motor
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Motor Voltage
          2. 9.2.1.2.2 Motor Current
        3. 9.2.1.3 Stall Detection
          1. 9.2.1.3.1 Detailed Design Procedure
            1. 9.2.1.3.1.1 Hardware Stall Detection Application Description
              1. 9.2.1.3.1.1.1 Hardware Stall Detection Timing
              2. 9.2.1.3.1.1.2 Hardware Stall Threshold Selection
            2. 9.2.1.3.1.2 Software Stall Detection Application Description
              1. 9.2.1.3.1.2.1 Software Stall Detection Timing
              2. 9.2.1.3.1.2.2 Software Stall Threshold Selection
        4. 9.2.1.4 Application Curves
        5. 9.2.1.5 Thermal Performance
          1. 9.2.1.5.1 Steady-State Thermal Performance
          2. 9.2.1.5.2 Transient Thermal Performance
  11. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance
  12. 11Layout
    1. 11.1 Layout Guidelines
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

GUID-20220419-SS0I-G9BW-CDPK-669PHGVKF3SV-low.svgFigure 6-1 DSG Package(WSON)Top View
GUID-20220419-SS0I-KPLG-4DWC-W2QCHDDW5SX4-low.svgFigure 6-2 RTE Package(WQFN)Top View
Table 6-1 Pin Functions
PINTYPEDESCRIPTION
NAMEDSGRTE
GND

4

9

PWRDevice ground. Connect to system ground.
IMODE—15ICurrent regulation mode configuration. Tri-level input. See Table 8-4.
IN1

6

13IControls the H-bridge output. Has internal pulldown. Logic input. See Table 8-2.
IN2

5

12IControls the H-bridge output. Has internal pulldown. Logic input. See Table 8-2.
IPROPI

8

1PWRAnalog current output proportional to load current. See Section 8.4.2.1.
nFAULT—

4

ODFault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. Connect to nSTALL pin to reduce number of external components. See Section 8.4.4.
nSTALL—

3

ODStall detection enable and stall indicator output. Pulled low during a stall condition. Connect an external pullup resistor for open-drain operation. Connect to nFAULT pin to reduce number of external components. Connect to GND to disable stall detection. See Section 8.4.3.
OUT1

2

6OH-bridge output. Connect directly to the motor or other inductive load.
OUT2

3

8OH-bridge output. Connect directly to the motor or other inductive load.
PGND—7PWRDevice power ground. Connect to system ground.
SMODE—

11

IStall detection response configuration. Tri-level input. See Table 8-6.
TINRUSH—

10

OSets timing for stall detection to ignore motor inrush current. Connect to a ceramic capacitor to system ground. See Section 8.4.3.
VCC—

2

PWRLogic power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor rated for VCC.
VM

1

5PWRMotor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM.
VREF—16IAnalog input to set current regulation and stall detection level. For the DSG package, VREF is internally fixed at 510 mV. For information on current regulation, see Section 8.4.2.2. For more information on stall detection, see Section 8.4.3.

GAINSEL

7

14

I

Configures IPROPI gain factor depeding on the output current range. Tri-level input.

PAD———Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes.