SLVSGV9 august   2023 DRV8213

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Diagrams
    7. 7.7 Typical Operating Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 External Components
    4. 8.4 Feature Description
      1. 8.4.1 Bridge Control
      2. 8.4.2 Current Sense and Regulation (IPROPI)
        1. 8.4.2.1 Current Sensing and Current Mirror Gain Selection
        2. 8.4.2.2 Current Regulation
      3. 8.4.3 Hardware Stall Detection
      4. 8.4.4 Protection Circuits
        1. 8.4.4.1 Overcurrent Protection (OCP)
        2. 8.4.4.2 Thermal Shutdown (TSD)
        3. 8.4.4.3 VM Undervoltage Lockout (UVLO)
    5. 8.5 Device Functional Modes
      1. 8.5.1 Active Mode
      2. 8.5.2 Low-Power Sleep Mode
      3. 8.5.3 Fault Mode
    6. 8.6 Pin Diagrams
      1. 8.6.1 Logic-Level Inputs
      2. 8.6.2 Tri-Level Input
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Brushed DC Motor
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Motor Voltage
          2. 9.2.1.2.2 Motor Current
        3. 9.2.1.3 Stall Detection
          1. 9.2.1.3.1 Detailed Design Procedure
            1. 9.2.1.3.1.1 Hardware Stall Detection Application Description
              1. 9.2.1.3.1.1.1 Hardware Stall Detection Timing
              2. 9.2.1.3.1.1.2 Hardware Stall Threshold Selection
            2. 9.2.1.3.1.2 Software Stall Detection Application Description
              1. 9.2.1.3.1.2.1 Software Stall Detection Timing
              2. 9.2.1.3.1.2.2 Software Stall Threshold Selection
        4. 9.2.1.4 Application Curves
        5. 9.2.1.5 Thermal Performance
          1. 9.2.1.5.1 Steady-State Thermal Performance
          2. 9.2.1.5.2 Transient Thermal Performance
  11. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance
  12. 11Layout
    1. 11.1 Layout Guidelines
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
9.2.1.3.1.1 Hardware Stall Detection Application Description

The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in Figure 9-5. The DRV8213 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The capacitor on the TINRUSH pin sets the timing, tINRUSH, so the DRV8213 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8213 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nSTALL pulls low to indicate the stall event to the microcontroller. Section 8.4.3 provides full details for configuring the stall detection feature.

GUID-20220426-SS0I-NX0S-JNX7-5LKQ9WL1SL14-low.svgFigure 9-4 Example timing diagram for hardware stall detection

Table 9-2 summarizes stall detection configuration.

Table 9-2 Summary table for hardware stall detection pin configuration
nSTALLTINRUSHSMODEDescription
GNDZ

X

Stall detection disabled. Float TINRUSH. If IMODE = Z, current regulation occurs at all times when VIPROPI ≥ VVREF.
Pull-up resistor to VCCGNDXTI does not recommend this configuration. tINRUSH corresponds to approximately 6.7s. Device continuously sources 10 uA out of TINRUSH pin into GND. If IMODE = Z, current regulation occurs when VIPROPI ≥ VVREF.
Capacitor to GND0Latched disable with indication: the OUTx pins disable and the nSTALL pin pulls low after tINRUSH when VIPROPI ≥ VVREF.
1

/ Z

Indication only: the OUTx pins remain active and the nSTALL pin pulls low after tINRUSH when VIPROPI ≥ VVREF.

Z

X

TI does not recommend this configuration. Floating TINRUSH pin effectively sets tINRUSH = 0 seconds.

The device responds according to the settings of SMODE and IMODE at all times when VIPROPI ≥ VVREF.

VCCXTI does not recommend this configuration. Tying TINRUSH to a voltage higher than 1 V effectively sets tINRUSH = 0 seconds. The device draws excessive current from the voltage source due to the TINRUSH discharge path being on.