Design of all aspects of the LMK3H0102 is straightforward, and software support is available to assist in frequency planning and part programming. This design procedure gives a straightforward outline of the process.

1. Frequency Planning
   1. The first step of designing an LMK3H0102 configuration is to determine the FOD frequencies that are required to generate the required output frequencies. The process is as such:
      1. If the output frequencies are greater than 200 MHz, the frequencies must both be the same, and cannot use SSC. If the frequencies are different, or require SSC, then this frequency plan cannot be supported by the device.
         • In the case of two identical frequencies greater than 200 MHz, the edge combiner must be enabled, the FOD divider values must match, and REF_CLK, if used, can be sourced from either FOD.
      2. If both output frequencies are the same, and have the same SSC settings (that is, both use SSC or both do not use SSC), only one FOD is required.
      3. If both output frequencies are different, but have the same SSC settings, the outputs can share an FOD to conserve current. If both frequencies can be generated from dividing a single valid FOD frequency by the channel divider options, then the second FOD can be disabled. Otherwise, both FODs must be used. If both outputs require SSC, then this frequency plan cannot be supported by the LMK3H0102 device.
      4. If one output requires SSC and the other does not, then the SSC output must use FOD0 and the non-SSC output must use FOD1.
   2. If SSC is being used, determine whether or not a preconfigured down-spread modulation, a custom down-spread modulation, or a center-spread modulation is required for the application. If a custom configuration is required, follow the steps outlined in Spread-Spectrum Clocking.
   3. Set the digital clock divider such that the digital clock frequency is as close to 50 MHz as possible.
   4. Determine the REF_CTRL pin functionality. If this is used as an additional LVCMOS reference clock, verify that the desired frequency can be generated based on the FOD0 and FOD1 frequencies, as the divider range for the REF_CLK output is /2, /4, or /8 only.
      1. Keep in mind that if SSC is used on FOD0, and the REF_CLK source is FOD0, this output now has SSC as well.
2. Setting the Output Formats
   1. The output formats that are required are based upon the clock format needed in the system. For PCIe applications, this is most often a 100-MHz LP-HCSL clock. The internal termination resistance value must be chosen such that the impedance matches the input impedance of the receiver. Note that the termination scheme is different for AC-LVDS and DC-LVDS - an AC-LVDS receiver requires an AC-LVDS output from the LMK3H0102.
   2. For differential outputs, the slew rate is selectable, from the slowest range (1.4 V/ns to 2.5 V/ns) to the fastest range (2.3 V/ns to 3.4 V/ns).
   3. For LP-HCSL outputs of either termination scheme, the amplitude is selectable between 625 mV and 885 mV.
   4. For LVCMOS outputs, the P and N phases can be in phase, opposite, or individually enabled or disabled. This allows for the generation of up to five LVCMOS clocks between OUT0, OUT1, and the REF_CTRL pin.
      1. For LVCMOS outputs, the VDDO_x voltage MUST match the VDD voltage if VDD is 1.8 V or 2.5 V.
3. Output Enable Behavior
   1. The output enable pin is active low by default, with an internal pulldown resistor to GND. If this functionality is not desired, then OE_PIN_POLARITY can be set to '0' to change the behavior of the OE pin to active-high. If this is done, the internal pulldown is disabled, and an internal pullup to VDD is used.
   2. Determine whether or not both outputs being disabled means that the device enters low-power mode. While this is able to conserve current, low-power mode is not recommended for any applications where the clocks must turn back on quickly, such as PCIe clocking.

For the PCIe example, the following settings are required:

1. One FOD can be used to generate both LP-HCSL outputs. As such, FOD0 can be set to have an output frequency of 200 MHz, with Channel Divider 0 set to divide by two. Alternatively, FOD0 can be set to 400 MHz with a divider by four. Both configurations are valid. Both output drivers select Channel Divider 0, and are both set to LP-HCSL.
   1. DIG_CLK_N_DIV must be set to two to set the state machine clock properly. The state machine clock must be as close to 50 MHz as possible without exceeding this frequency. Equation 9 shows the relationship between the digital state machine frequency, the frequency selected by the CH0_FOD_SEL multiplexer, and the DIG_CLK_N_DIV field. Write the DIG_CLK_N_DIV field only while the device is in the low power state.
2. FOD1 can be used to generate the 33-MHz LVCMOS clock, as FOD0 cannot support 33 MHz in addition to 100 MHz. The REF_CLK divider options are divides by two, four, or eight. While dividing by two does not yield any valid configurations, both 132 MHz with a divide by four and 264 MHz with a divide by 8 are valid options.

where F_DIG is the digital state machine clock frequency and F_{CH0_FOD_SEL} is the frequency selected by the CHO_FOD_SEL multiplexer