SNAS847 November   2023 LMK3H0102

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Interface Specification
  7. 6 Differential Voltage Measurement Terminology
  8. 7 Parameter Measurement Information
    1. 7.1 Output Format Configurations
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Block-Level Description
      2. 8.3.2 Device Configuration Control
      3. 8.3.3 OTP Mode
      4. 8.3.4 I2C Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Fail-Safe Inputs
      2. 8.4.2 Fractional Output Dividers
        1. 8.4.2.1 FOD Operation
        2. 8.4.2.2 Edge Combiner
        3. 8.4.2.3 Digital State Machine
        4. 8.4.2.4 Spread-Spectrum Clocking
        5. 8.4.2.5 Integer Boundary Spurs
      3. 8.4.3 Output Behavior
        1. 8.4.3.1 Output Format Selection
          1. 8.4.3.1.1 Output Format Types
            1. 8.4.3.1.1.1 LP-HCSL Termination
        2. 8.4.3.2 Output Slew Rate Control
        3. 8.4.3.3 REF_CTRL Operation
      4. 8.4.4 Output Enable
        1. 8.4.4.1 Output Enable Control
        2. 8.4.4.2 Output Enable Polarity
        3. 8.4.4.3 Individual Output Enable
        4. 8.4.4.4 Output Disable Behavior
      5. 8.4.5 Device Default Settings
    5. 8.5 Programming
      1. 8.5.1 I2C Serial Interface
      2. 8.5.2 One-Time Programming Sequence
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application Block Diagram Examples
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Example: Changing Output Frequency
      5. 9.2.5 Crosstalk
      6. 9.2.6 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-Up Sequencing
      2. 9.3.2 Decoupling Power Supply Inputs
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device Registers
    1. 10.1 Register Maps
      1. 10.1.1  R0 Register (Address = 0x0) [reset = 0x0861]
      2. 10.1.2  R1 Register (Address = 0x1) [reset = 0x5599]
      3. 10.1.3  R2 Register (Address = 0x2) [reset = 0xC28F]
      4. 10.1.4  R3 Register (Address = 0x3) [reset = 0x1801]
      5. 10.1.5  R4 Register (Address = 0x4) [reset = 0x0000]
      6. 10.1.6  R5 Register (Address = 0x5) [reset = 0x0000]
      7. 10.1.7  R6 Register (Address = 0x6) [reset = 0x2AA0]
      8. 10.1.8  R7 Register (Address = 0x7) [reset = 0x6503]
      9. 10.1.9  R8 Register (Address = 0x8) [reset = 0xC28F]
      10. 10.1.10 R9 Register (Address = 0x9) [reset = 0x0066]
      11. 10.1.11 R10 Register (Address = 0xA) [reset = 0x0010]
      12. 10.1.12 R11 Register (Address = 0xB) [reset = 0x0000]
      13. 10.1.13 R12 Register (Address = 0xC) [reset = 0xE800]
      14. 10.1.14 R146 Register (Address = 0x92) [reset = 0x0000]
      15. 10.1.15 R147 Register (Address = 0x93) [reset = 0x0000]
      16. 10.1.16 R148 Register (Address = 0x94) [reset = 0x0000]
      17. 10.1.17 R238 Register (Address = 0xEE) [reset = 0x0000]
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Package Option Addendum
    2. 13.2 Tape and Reel Information

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RER|16
Thermal pad, mechanical data (Package|Pins)

8.4.2.1 FOD Operation

The internal BAW resonator is divided down by one or two Fractional Output Dividers (FODs). FOD0 has an SSC generator and FOD1 does not have an SSC generator. If both OUT0 and OUT1 must be SSC clocks, the two clocks must be sourced by FOD0. If one SSC clock and one non-SSC clock are required at the same time, then FOD0 is enabled for the SSC clock and FOD1 is enabled for the non-SSC clock. If neither output clock requires SSC, then either FOD can be used.

Note: TI recommends that FOD0 be used as the default FOD if only one FOD is needed for an application. If both FODs are in use, TI recommends using FOD0 with OUT0 and FOD1 with OUT1.

The maximum frequency that can be generated at the clock outputs by a single FOD is 200 MHz, as the minimum channel divider value is a divide by two. To generate a greater than 200 MHz output, the edge combiner is used, bypassing the channel dividers. This requires that both FODs are enabled and have the same integer divider and fractional numerator values, and the same gain calibration values. When one of the outputs exceeds 200 MHz, the other output can only select the shared FOD frequency divided by one of the channel divider values, or be the FOD frequency. Below 200 MHz, the two FODs can be configured independently so that OUT0 and OUT1 can have different frequencies. TI recommends sourcing from a single FOD whenever possible to make sure that OUT0 and OUT1 have a deterministic phase relationship.

The FODs in the LMK3H0102 can be configured to accommodate various output frequencies through I2C programming, or in the absence of programming, the one-time programmed (OTP) settings. The FODs can be configured by setting the integer (FODx_N_DIV) and fractional (FODx_NUM) divide values. Table 8-4 shows the register locations for these fields for each FOD.

Table 8-4 FOD Integer and Numerator Divide Locations
Field Register
FOD0_N_DIV R0[9:3]
FOD0_NUM[23:16] R1[15:8]
FOD0_NUM[15:0] R2[15:0]
FOD1_N_DIV R3[15:9]
FOD1_NUM[23:16] R6[12:5]
FOD1_NUM[15:0] R8[15:0]

An example of how to set the integer and numerator divide values is shown in Equation 1 and Equation 2.

Equation 1. FODx_N_DIV = floor(FBAW/FFOD)

where:

  • FODx_N_DIV: Integer portion of the FOD divide value (7 bits, 6 to 24)
  • FBAW: BAW frequency, 2467 MHz plus offset, described in further detail below
  • FFOD: Desired FOD frequency (100 MHz to 400 MHz)

Equation 2. FODx_NUM = int(((FBAW/FFOD) - FODx_N_DIV) × 224)

where FODx_NUM is the fractional portion of the FOD divide value (24 bits, that is 0 to 16777215).

The output frequency (FOUT) is related to the FOD frequency as given in Equation 3, or is equal to the FOD frequency when the edge combiner is enabled. OUTDIV can be 2, 4, 6, 8, 10, 20, or 40.

Equation 3. FOUT = FFOD/OUTDIV

Use Equation 4 to calculate the actual value of the BAW frequency for a device. Users can find the value of BAWFREQ_OFFSET_FIXEDLUT by reading R238, which is a signed 16-bit value.

Equation 4. FBAW = 2467 MHz × (1 + (BAWFREQ_OFFSET_FIXEDLUT × 128E-9))