SNAS847 November 2023 LMK3H0102
ADVANCE INFORMATION
Refer to the PDF data sheet for device specific package drawings
In this mode, I2C is enabled and the SCA and SDL pins function as the I2C clock and I2C data pins, respectively. Table 8-3 shows the four default I2C addresses selectable by the FMT_ADDR pin. The 5 MSBs of the I2C address are set in the upper five bits of I2C_ADDR (R12[14:8]).
If I2C_ADDR_LSB_SEL (R12[15]) = 0, then the FMT_ADDR pin is ignored, and the I2C address is solely determined by I2C_ADDR.
REF_CTRL PIN(1) | FMT_ADDR PIN | I2C ADDRESS(2) |
---|---|---|
High | X | N/A (I2C disabled) |
Low | 0 | 0x68 / 0xD0 |
Low | 1 | 0x69 / 0xD2 |
Low | Tied to SDA | 0x6A / 0xD4 |
Low | Tied to SCL | 0x6B / 0xD8 |
When changing the registers of the device, first set PDN to '1', write to the device registers, then set PDN to '0'.Figure 8-4 shows this process.