Figure 8-2 shows the relationships between device states, the configuration pins, device initialization, and device operational modes. OTP mode is entered when the REF_CTRL pin is pulled high at start-up. I²C mode is entered when the REF_CTRL pin is pulled low at start-up. In OTP mode, the state of the OTP_SEL0/SCL and OTP_SEL1/SDA pins determines the OTP page that is loaded into the active registers. The device is one-time programmable, meaning that the register settings stored into the internal EFUSE cannot be changed. The device can be transitioned from OTP to I²C mode, or vice versa, by changing the state of the REF_CTRL pin, then triggering a device power cycle by pulling VDD low, then high again. In OTP mode, a change in the level of the OTP_SEL0 or OTP_SEL1 pins, followed by pulling the REF_CTRL pin high, will dynamically change the active OTP page. The time between the first OTP_SEL pin change and pulling REF_CTRL high must be less than 350 us, otherwise the device will enter I2C Mode.

In I²C mode, the state of the FMT_ADDR pin can determine the I²C address of the device, with the OTP_SEL0/SCL and OTP_SEL1/SDA pins re-purposed as I²C clock and data pins, respectively. In I²C mode, the host can update the active device registers. If using a configuration different than the programmed configuration, the registers must be written after each power cycle.

The device can be placed into a low power state by setting the PDN bit (R10[1]) to '1'. Clearing the PDN bit takes the device out of the low power state. If DEV_IDLE_STATE_SEL bit (R10[4]) is a '0' and the outputs are disabled, the device enters the low power state. Entering the low power state is required for changing the frequency of the FOD used by Channel 0, changing the SSC configuration, and changing the output format. TI recommends performing register writes within this low power state. Set the OTP_AUTOLOAD_DIS (R10[2]) bit to a '1' to prevent automatic loading of OTP Page 0 prior to setting PDN to '0'.

There are two fields that determine the state of the device when coming out of the low power state. PIN_RESAMPLE_DIS (R10[3]) controls whether or not the FMT_ADDR, OTP_SEL0/SCL, OTP_SEL1/SDA, and REF_CTRL pins are resampled when exiting the low power state. If the pins are resampled, the device can be transitioned into OTP mode if the REF_CTRL pin is pulled high. Set this bit to a '1' to disable this functionality. OTP_AUTOLOAD_DIS controls whether or not the contents of OTP Page 0 are loaded into the device registers when exiting the low power state. If OTP_AUTOLOAD_DIS bit is a '1' and PIN_RESAMPLE_DIS is a '1', then the register contents do not change. If OTP_AUTOLOAD_DIS bit is a '0' and PIN_RESAMPLE_DIS is a '1', then the contents of OTP Page 0 are loaded to the registers. If PIN_RESAMPLE_DIS is a '0' and REF_CTRL is pulled high, then the device enters OTP Mode. In this case, OTP_SEL0/SCL and OTP_SEL1/SDA control the OTP page loaded into the device registers.

Figure 8-2 LMK3H0102 Device Mode Diagram

In I²C Mode, the device registers are from the contents of OTP Page 0. In OTP mode, these values come from one of the four OTP pages, selectable based on the state of the OTP_SELx pins on start-up. Figure 8-3 shows interface and control blocks within the LMK3H0102, with the arrows referring to read and write access from the different embedded memories.

Figure 8-3 LMK3H0102 Interface and Control Blocks