SNAS847 November 2023 LMK3H0102
ADVANCE INFORMATION
Refer to the PDF data sheet for device specific package drawings
The digital state machine of the LMK3H0102 has a clock that originates from one of the FODs. The FOD selected by CH0_FOD_SEL (R3[4]) drives the input to the state machine clock divider. The total divide value is the DIG_CLK_N_DIV (R0[9:3]) field plus two. Set DIG_CLK_N_DIV such that the FOD frequency divided by the total state machine clock divide value is between 40 MHz and 50 MHz. The divider value used to set this clock is equal to the value stored in . As an example, if the frequency of FOD0 is 200 MHz, and CH0_FOD_SEL is a '0', then DIG_CLK_N_DIV must be set to '2', as 200 MHz divided by 4 is 50 MHz.