SNAS847 November   2023 LMK3H0102

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Interface Specification
  7. 6 Differential Voltage Measurement Terminology
  8. 7 Parameter Measurement Information
    1. 7.1 Output Format Configurations
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Block-Level Description
      2. 8.3.2 Device Configuration Control
      3. 8.3.3 OTP Mode
      4. 8.3.4 I2C Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Fail-Safe Inputs
      2. 8.4.2 Fractional Output Dividers
        1. 8.4.2.1 FOD Operation
        2. 8.4.2.2 Edge Combiner
        3. 8.4.2.3 Digital State Machine
        4. 8.4.2.4 Spread-Spectrum Clocking
        5. 8.4.2.5 Integer Boundary Spurs
      3. 8.4.3 Output Behavior
        1. 8.4.3.1 Output Format Selection
          1. 8.4.3.1.1 Output Format Types
            1. 8.4.3.1.1.1 LP-HCSL Termination
        2. 8.4.3.2 Output Slew Rate Control
        3. 8.4.3.3 REF_CTRL Operation
      4. 8.4.4 Output Enable
        1. 8.4.4.1 Output Enable Control
        2. 8.4.4.2 Output Enable Polarity
        3. 8.4.4.3 Individual Output Enable
        4. 8.4.4.4 Output Disable Behavior
      5. 8.4.5 Device Default Settings
    5. 8.5 Programming
      1. 8.5.1 I2C Serial Interface
      2. 8.5.2 One-Time Programming Sequence
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application Block Diagram Examples
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Example: Changing Output Frequency
      5. 9.2.5 Crosstalk
      6. 9.2.6 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-Up Sequencing
      2. 9.3.2 Decoupling Power Supply Inputs
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device Registers
    1. 10.1 Register Maps
      1. 10.1.1  R0 Register (Address = 0x0) [reset = 0x0861]
      2. 10.1.2  R1 Register (Address = 0x1) [reset = 0x5599]
      3. 10.1.3  R2 Register (Address = 0x2) [reset = 0xC28F]
      4. 10.1.4  R3 Register (Address = 0x3) [reset = 0x1801]
      5. 10.1.5  R4 Register (Address = 0x4) [reset = 0x0000]
      6. 10.1.6  R5 Register (Address = 0x5) [reset = 0x0000]
      7. 10.1.7  R6 Register (Address = 0x6) [reset = 0x2AA0]
      8. 10.1.8  R7 Register (Address = 0x7) [reset = 0x6503]
      9. 10.1.9  R8 Register (Address = 0x8) [reset = 0xC28F]
      10. 10.1.10 R9 Register (Address = 0x9) [reset = 0x0066]
      11. 10.1.11 R10 Register (Address = 0xA) [reset = 0x0010]
      12. 10.1.12 R11 Register (Address = 0xB) [reset = 0x0000]
      13. 10.1.13 R12 Register (Address = 0xC) [reset = 0xE800]
      14. 10.1.14 R146 Register (Address = 0x92) [reset = 0x0000]
      15. 10.1.15 R147 Register (Address = 0x93) [reset = 0x0000]
      16. 10.1.16 R148 Register (Address = 0x94) [reset = 0x0000]
      17. 10.1.17 R238 Register (Address = 0xEE) [reset = 0x0000]
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Package Option Addendum
    2. 13.2 Tape and Reel Information

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RER|16
Thermal pad, mechanical data (Package|Pins)

9.2.5 Crosstalk

Performance degradation can occur in the LMK3H0102 due to crosstalk in the device when the outputs are operating at different frequencies. Table 9-1 displays the performance of the LMK3H0102 outputs for common LVCMOS frequencies. Contact TI for measurement of additional combinations for impact of crosstalk on output performance.

Table 9-1 LMK3H0102 LVCMOS Output Crosstalk (1)
FOD0 Frequency (MHz) FOD1 Frequency (MHz)s OUT0 Frequency (MHz) (2) OUT1 Frequency (MHz)(2) Typical OUT0 RMS Jitter (fs) (3) Typical OUT1 RMS Jitter (fs) (3)
240 240 24 24 220 226
240 250 24 25 852 716
240 270 24 27 457 371
240 200 24 50 832 779
250 240 25 24 784 717
250 250 25 25 340 308
250 270 25 27 757 787
250 200 25 50 215 516
270 240 27 24 429 367
270 250 27 25 913 641
270 270 27 27 310. 285
270 200 27 50 865 930
200 240 50 24 806 548
200 250 50 25 559 287
200 270 50 27 913 704
200 200 50 50 403 348
(1) Measured over 25 °C to 105 °C using differential LVCMOS output formats using VDD = VDDO_x = 3.3 V, no SSC.
(2) OUT0 and OUT1 are generated using FOD0 and FOD1, respectively.
(3) RMS Jitter measured over the 12 kHz to 5 MHz integration bandwidth.