SLASEC8C February   2017  – February 2023 PGA460-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Internal Supply Regulators Characteristics
    6. 6.6  Transducer Driver Characteristics
    7. 6.7  Transducer Receiver Characteristics
    8. 6.8  Analog to Digital Converter Characteristics
    9. 6.9  Digital Signal Processing Characteristics
    10. 6.10 Temperature Sensor Characteristics
    11. 6.11 High-Voltage I/O Characteristics
    12. 6.12 Digital I/O Characteristics
    13. 6.13 EEPROM Characteristics
    14. 6.14 Timing Requirements
    15. 6.15 Switching Characteristics
    16. 6.16 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-Supply Block
      2. 7.3.2  Burst Generation
        1. 7.3.2.1 Using Center-Tap Transformer
        2. 7.3.2.2 Direct Drive
        3. 7.3.2.3 Other Configurations
      3. 7.3.3  Analog Front-End
      4. 7.3.4  Digital Signal Processing
        1. 7.3.4.1 Ultrasonic Echo—Band-Pass Filter
        2. 7.3.4.2 Ultrasonic Echo–Rectifier, Peak Hold, Low-Pass Filter, and Data Selection
        3. 7.3.4.3 Ultrasonic Echo—Nonlinear Scaling
        4. 7.3.4.4 Ultrasonic Echo—Threshold Data Assignment
        5. 7.3.4.5 Digital Gain
      5. 7.3.5  System Diagnostics
        1. 7.3.5.1 Device Internal Diagnostics
      6. 7.3.6  Interface Description
        1. 7.3.6.1 Time-Command Interface
          1. 7.3.6.1.1 RUN Commands
          2. 7.3.6.1.2 CONFIGURATION/STATUS Command
        2. 7.3.6.2 USART Interface
          1. 7.3.6.2.1 USART Asynchronous Mode
            1. 7.3.6.2.1.1 Sync Field
            2. 7.3.6.2.1.2 Command Field
            3. 7.3.6.2.1.3 Data Fields
            4. 7.3.6.2.1.4 Checksum Field
            5. 7.3.6.2.1.5 PGA460-Q1 UART Commands
            6. 7.3.6.2.1.6 UART Operations
              1. 7.3.6.2.1.6.1 No-Response Operation
              2. 7.3.6.2.1.6.2 Response Operation (All Except Register Read)
              3. 7.3.6.2.1.6.3 Response Operation (Register Read)
            7. 7.3.6.2.1.7 Diagnostic Field
            8. 7.3.6.2.1.8 USART Synchronous Mode
          2. 7.3.6.2.2 One-Wire UART Interface
          3. 7.3.6.2.3 Ultrasonic Object Detection Through UART Operations
        3. 7.3.6.3 In-System IO-Pin Interface Selection
      7. 7.3.7  Echo Data Dump
        1. 7.3.7.1 On-Board Memory Data Store
        2. 7.3.7.2 Direct Data Burst Through USART Synchronous Mode
      8. 7.3.8  Low-Power Mode
        1. 7.3.8.1 Time-Command Interface
        2. 7.3.8.2 UART Interface
      9. 7.3.9  Transducer Time and Temperature Decoupling
        1. 7.3.9.1 Time Decoupling
        2. 7.3.9.2 Temperature Decoupling
      10. 7.3.10 Memory CRC Calculation
      11. 7.3.11 Temperature Sensor and Temperature Data-Path
      12. 7.3.12 TEST Pin Functionality
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 UART and USART Communication Examples
    6. 7.6 Register Maps
      1. 7.6.1 EEPROM Programming
      2. 7.6.2 Register Map Partitioning and Default Values
      3. 7.6.3 REGMAP Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Transducer Types
    2. 8.2 Typical Applications
      1. 8.2.1 Transformer-Driven Method
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Transducer Driving Voltage
          2. 8.2.1.2.2 Transducer Driving Frequency
          3. 8.2.1.2.3 Transducer Pulse Count
          4. 8.2.1.2.4 Transformer Turns Ratio
          5. 8.2.1.2.5 Transformer Saturation Current and Main Voltage Rating
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Direct-Driven (Transformer-Less) Method
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.12 TEST Pin Functionality

The PGA460-Q1 TEST pin serves multiple purposes including:

  • Allows the user to extract internal signals from the PGA460-Q1 device.
  • Selects the output voltage of the digital pins which enables a 3.3-V MCU or a 5-V MCU to be connected to the device without using any external voltage translators. The RXD, TXD, SCLK, DECPL, and TEST pins are affected by this selection.

Internal signals on the TEST pin can be extracted by selecting a predefined signal through the internal test mux. The TEST_MUX register parameter is used to select this signal. Table 7-5 lists the possible PGA460-Q1 internal signals that are output at the TEST pin.

Table 7-5 Internal Signals that can be Muxed out on the TEST Pin
TEST_MUX VALUESIGNAL NAMETYPEDESCRIPTION
0x00Hi-Z (disabled)AnalogThe TEST pin is in the high impedance state
0x01ASC OutputSAR ADC input after the ADC buffer
0x02Reserved
0x03Reserved
0x048MHz ClockDigital8-MHz clock output from PGA460-Q1
0x05ADC Sample Clock1-µs ADC sample Clock
0x06Reserved
0x07Reserved

When used as an analog test-mux output, the TEST pin output voltage can change from 0 V to 1.8 V while the common mode voltage is set to 0.9 V.

The digital voltage-level selection performed by the TEST pin is executed at device power up. On power-up, the device checks the level of the TEST pin. If the level is low, the digital output pins operate at 3.3 V. If the TEST pin is tied high (3.3 V or 5 V are both considered high state), the digital output pins operate at a 5 V. This condition is latched in the PGA460-Q1 device so that the test mux can further use the TEST pin as previously described. If the application requires that a 5-V digital output is used and a test mux output must be extracted from the PGA460-Q1 device, then a weak pullup resistor on the TEST pin can be connected as shown in #X2613.

GUID-6730F430-C83E-41E2-BEBC-01CBFB79CBEE-low.gifFigure 7-40 Test Pin Test Mux Output Application

As shown in #X2613, the resistor (RPU) is connected to a permanent power supply and a current path to ground is generated through the RPU resistor and the 800-kΩ internal resistance. This configuration is no problem for the system; however, it might cause a small quiescent-current increase in applications that require the use of the PGA460-Q1 low-power mode to preserve energy. In this case, the TEST pin can be connected to a GPIO pin on the external MCU that can output a logic low or high state on the TEST pin to select the voltage level at device start-up and later disable the GPIO output to preserve energy or reconfigure the GPIO as an input in case the MCU uses any of the PGA460-Q1 test output signals. The external pullup resistor is only required for CMOS 5-V UART communication and is not required for 3-V communication.