SLLSFE2 June   2019 SN65HVDA1040B-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Power Dissipation Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Operating Modes
        1. 8.3.1.1 Bus States by Mode
        2. 8.3.1.2 Normal Mode
        3. 8.3.1.3 Standby Mode and RXD Wake-Up Request
      2. 8.3.2 Protection Features
        1. 8.3.2.1 TXD Dominant State Time-Out
        2. 8.3.2.2 Thermal Shutdown
        3. 8.3.2.3 Undervoltage Lockout and Unpowered Device
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Using With 3.3-V Microcontrollers
      2. 9.1.2 Using SPLIT With Split Termination
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Bus Loading, Length, and Number of Nodes
        2. 9.2.1.2 CAN Termination
        3. 9.2.1.3 Loop Propagation Delay
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Transient Voltage Suppresser (TVS) Diodes
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 ESD Protection
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

over recommended operating conditions including operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
SUPPLY
ICC 5-V supply current Standby mode STB at VCC, VI = VCC 6 12 µA
Dominant VI = 0 V, 60-Ω load, STB at 0 V 50 70 mA
Recessive VI = VCC, No load, STB at 0 V 6 10
UVVCC Undervoltage reset threshold 2.8 4 V
DRIVER
VO(D) Bus output voltage (dominant) CANH VI = 0 V, STB at 0 V, RL = 60 Ω,
See Figure 3 and Figure 16 		2.9 3.4 4.5 V
CANL 0.8 1.75
VO(R) Bus output voltage (recessive) VI = 3 V, STB at 0 V, RL = 60 Ω,
See Figure 3 and Figure 16 		2 2.5 3 V
VO Bus output voltage (standby mode) STB at Vcc, RL = 60 Ω,
See Figure 3 and Figure 16 		–0.1 0.1 V
VOD(D) Differential output voltage (dominant) VI = 0 V, RL = 60 Ω, STB at 0 V,
See Figure 3, Figure 16, and Figure 4 		1.5 3 V
VI = 0 V, RL = 45 Ω, STB at 0 V,
See Figure 3, Figure 16, and Figure 4 		1.4 3
VOD(R) Differential output voltage (recessive) VI = 3 V, STB at 0 V, RL = 60 Ω,
See Figure 3 and Figure 16 		–0.012 0.012 V
VI = 3 V, STB at 0 V, No load –0.5 0.05
VSYM Output symmetry (dominant or recessive) (VO(CANH) + VO(CANL)) STB at 0 V, RL = 60 Ω, See Figure 14 0.9 VCC VCC 1.1 VCC V
VOC(ss) Steady-state common-mode output voltage STB at 0 V, RL = 60 Ω, See Figure 9 2 2.5 3 V
ΔVOC(ss) Change in steady-state common-mode output voltage STB at 0 V, RL = 60 Ω, See Figure 9 30 mV
VIH High-level input voltage, TXD input 2 V
VIL Low-level input voltage, TXD input 0.8 V
IIH High-level input current, TXD input VI at VCC –2 2 µA
IIL Low-level input current, TXD input VI at 0 V –50 –10 µA
IO(off) Power-off TXD output current VCC at 0 V, TXD at 5 V 1 µA
IOS(ss) Short-circuit steady-state output current, Dominant VCANH = –12 V, CANL open, TXD = low,
See Figure 12 		–120 –85 mA
VCANH = 12 V, CANL open, TXD = low,
See Figure 12 		0.4 1
VCANL = –12 V, CANH open, TXD = low,
See Figure 12 		–1 –0.6
VCANL = 12 V, CANH open, TXD = low,
See Figure 12 		75 120
VCANH = 0 V, CANL open, TXD = low,
See Figure 12 		–100 –75
VCANL = 32 V, CANH open, , TXD = low,
See Figure 12 		75 125
IOS(ss) Short-circuit steady-state output current, Recessive –20 V ≤ VCANH ≤ 32 V, CANL open,
TXD = high, See Figure 12 		–10 10 mA
–20 V ≤ VCANL ≤ 32 V, CANH open,
TXD = high, See Figure 12 		–10 10
CO Output capacitance See receiver input capacitance
RECEIVER
VIT+ Positive-going input threshold voltage, high-speed mode STB at 0 V, See Table 1 800 900 mV
VIT– Negative-going input threshold voltage, high-speed mode STB at 0 V, See Table 1 500 650 mV
Vhys Hysteresis voltage (VIT+ – VIT–) 100 125 mV
VIT Input threshold voltage, standby mode STB at VCC 500 1150 mV
VOH High-level output voltage IO = –2 mA, See Figure 7 4 4.6 V
VOL Low-level output voltage IO = 2 mA, See Figure 7 0.2 0.4 V
II(off) Power-off bus input current (unpowered bus leakage current) CANH = CANL = 5 V,
VCC at 0 V, TXD at 0 V		 3 µA
IO(off) Power-off RXD leakage current VCC at 0 V, RXD at 5 V 20 µA
CI Input capacitance to ground (CANH or CANL) TXD at 3 V,
VI = 0.4 sin (4E6πt) + 2.5 V		 13 pF
CID Differential input capacitance TXD at 3 V, VI = 0.4 sin (4E6πt) 6 pF
RID Differential input resistance TXD at 3 V, STB at 0 V 30 80 kΩ
RIN Input resistance (CANH or CANL) TXD at 3 V, STB at 0 V 15 30 40 kΩ
RI(m) Input resistance matching
[1 – (RIN (CANH) / RIN (CANL))] × 100%		 V(CANH) = V(CANL) –3% 0% 3%
STB PIN
VIH High-level input voltage, STB input 2 V
VIL Low-level input voltage, STB input 0.8 V
IIH High-level input current STB at 2 V –10 0 µA
IIL Low-level input current STB at 0.8 V –10 0 µA
SPLIT PIN
VO Output voltage –250 µA < IO < 250 µA 0.3 VCC 0.5 VCC 0.7 VCC V
IO(stb) Leakage current, standby mode STB at 2 V, –12 V ≤ VO ≤ 12 V –5 5 µA
(1) All typical values are at 25°C with a 5-V supply.