SNIS214E june   2021  – july 2023 TMP114

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Device Comparison
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Interface Timing
    7. 7.7 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 1.2 V Compatible Logic Inputs
      2. 8.3.2 Cyclic Redundancy Check (CRC)
      3. 8.3.3 Temperature Limits
      4. 8.3.4 Slew Rate Warning
      5. 8.3.5 NIST Traceability
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Conversion Mode
      2. 8.4.2 Shutdown Mode
        1. 8.4.2.1 One-Shot Temperature Conversions
    5. 8.5 Programming
      1. 8.5.1 Temperature Data Format
      2. 8.5.2 I2C and SMBus Interface
      3. 8.5.3 Device Address
      4. 8.5.4 Bus Transactions
        1. 8.5.4.1 Auto-Increment
        2. 8.5.4.2 Writes
          1. 8.5.4.2.1 CRC Enabled Writes
        3. 8.5.4.3 Reads
          1. 8.5.4.3.1 CRC Enabled Reads
        4. 8.5.4.4 General Call Reset Function
        5. 8.5.4.5 Time-Out Function
        6. 8.5.4.6 Coexist on I3C MixedBus
        7. 8.5.4.7 Cyclic Redundancy Check Implementation
    6. 8.6 Register Map
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Separate I2C Pullup and Supply Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Equal I2C Pullup and Supply Voltage Application
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YMT|4
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Writes

To write on the I2C bus, the controller sends a START condition on the bus with the address of the target, as well as the last bit (the R/W bit) set to 0b, which signifies a write. The target acknowledges, letting the controller know it is ready. After this, the controller starts sending the control register data to the target until the controller has sent all the data necessary, and the controller terminates the transmission with a STOP condition.

Writes to read-only registers or register locations outside of the register map will be ignored. The TMP114 will still ACK when writing outside of the register map.

Figure 8-10 shows an example of writing a single word write communication.

GUID-20210113-CA0I-DKTJ-V6J5-K8FXDJP877N4-low.gif Figure 8-10 Write to Single Register

Multiple writes to the same register are also possible with the TMP114. Figure 8-11 shows how the controller can repeatedly write to the same register when the Auto-Increment bit in the control register is set to 0b.

GUID-20210113-CA0I-NFQP-SF0G-VL361WDLJWQX-low.svg Figure 8-11 Repeated Write to Single Register

The TMP114 also supports a continuous write to sequential registers. By setting the Auto-Increment bit in the control register to 1b, the TMP114 will increment the address pointer after each word of data is written to the device. This allows the controller to write multiple register values in the same transaction as shown in Figure 8-12. Currently this feature will not allow the controller to properly write to the Configuration register and it is recommended to use single register writes to the Configuration register.

GUID-20210113-CA0I-PFQR-Z87C-ZBS1BV38XWGJ-low.svg Figure 8-12 Burst Write to Multiple Registers