The internal PoE undervoltage lockout (UVLO) circuit holds the hotswap switch off before the PSE provides full voltage to the PD. This prevents the converter circuits from loading the PoE input during detection and classification. The converter circuits discharges C_DD, C_CC, and C_VB while the PD is unpowered. Thus V_VDD-RTN will be a small voltage until just after full voltage is applied to the PD, as seen in Figure 7-7.

The PSE drives the PD input voltage to the operating range once it has decided to power up the PD. When V_PD rises above the UVLO turnon threshold (V_UVLO-R, approximately 35.5 V) with RTN high, the TPS23755 enables the hotswap MOSFET with an approximately 140-mA (inrush) current limit. See the waveforms of Figure 7-8 for an example. Converter switching is disabled while C_DD charges and V_RTN falls from V_VDD to nearly V_VSS; however, the converter start-up circuit is allowed to charge C_CC. Once the inrush current falls about 10% below the inrush current limit, the PD control switches to the operational level (approximately 450 mA) and converter switching is permitted.

Converter switching is allowed if the PD is not in inrush current limit and the VCC under-voltage lockout (V_CUVR) circuit permits it. Continuing the start-up sequence shown in Figurer 7-7, V_VCC rises as the start-up current source charges C_CC and the converter switching is inhibited by the status of the VCC UVLO. The VB regulator powers the internal converter circuits as V_VCC rises.

Once V_VCC goes above its UVLO (nominally 8.25 V), the converter switching is enabled following the closed loop controlled soft-start sequence. Note that the startup current source capability is such that it can fully maintain V_VCC during the converter soft-start without requiring any significant C_CC capacitance, in 48 V input applications. At the end of the soft-start period, the startup current source is turned off. V_VCC falls as it powers the internal circuits including the switching MOSFET gate. If the converter control-bias output rises to support V_VCC before it falls to V_CUVF (nominally 6.1 V), a successful start-up occurs. Figure 7-7 shows a small droop in V_VCC while the output voltage rises smoothly and a successful start-up occurs.

Figure 7-8 Power Up and Start

The converter shuts off when V_VCC falls below its lower UVLO. This can happen when power is removed from the PD, or during a fault on a converter output rail. When one output is shorted, all the output voltages fall including the one that powers VCC. The control circuit discharges VCC until it hits the lower UVLO and turns off. A restart initiates if the converter turns off and there is sufficient VDD voltage. This type of operation is sometimes referred to as hiccup mode, which when combined with the soft-start provides robust output short protection by providing time-average heating reduction of the output rectifier.

Figure 7-9 illustrates the situation when there is severe overload at the main output which causes VCC hiccup. After VCC went below its UVLO due to the overload, the startup source is turned back on. Then, a new soft-start cycle is reinitiated, introducing a short pause before the output voltage is ramped up.

Figure 7-9 Restart Following Severe Overload at Main Output of Flyback DC-DC Converter

If V_VPD-VSS drops below the lower PoE UVLO (UVLO_R – UVLO_H, approximately 31 V), the hotswap MOSFET is turned off, but the converter still runs. The converter stops if V_VCC falls below the V_CUVF (nominally 6.1 V), the hotswap is in inrush current limit, the SST pin is pulled to ground, V_VDD-RTN falls below typically 7.7 V (approximately 0.75 V hysteresis) or the converter is in thermal shutdown.