The current-sense input for the DC-DC converter should be connected to the high side of the current-sense resistor of the switching MOSFET. The current-limit threshold, V_CSMAX, defines the voltage on CS above which the switching FET ON-time is terminated regardless of the voltage on COMP output.

Routing between the current-sense resistor and the CS pin must be short to minimize cross-talk from noisy traces such as DRAIN and CP, and to a lower degree to SRR and SRF.

Current-mode control requires addition of a compensation ramp to the sensed inductor (flyback transformer) current for stability at duty cycles near and over 50%. The TPS23755 has a maximum duty cycle limit of 78.5%, permitting the design of wide input-range flyback converters with a lower voltage stress on the output rectifiers. While the maximum duty cycle is 78.5%, converters may be designed that run at duty cycles well below this for a narrower, 36-V to 57-V range. The TPS23755 provides a fixed internal compensation ramp that suffices for most applications. R_S (see Figure 7-2) may be used if the internally provided slope compensation is not enough. It works with ramp current (I_PK = I_SL-EX, approximately 40 μA) that flows out of the CS pin when the MOSFET is on. The I_PK specification does not include the approximately 5-μA fixed current that flows out of the CS pin.

Most current-mode control papers and application notes define the slope values in terms of V_PP/T_S (peak ramp voltage / switching period); however, Electrical Characteristics: DC-DC Controller Section specifies the slope peak (V_SLOPE) based on the maximum duty cycle. Assuming that the desired slope, V_SLOPE-D (in mV/period), is based on the full period, compute R_S per Equation 1 where V_SLOPE, D_MAX, and I_SL-EX are from Electrical Characteristics: DC-DC Controller Section with voltages in mV, current in μA, and the duty cycle is unitless (for example, D_MAX = 0.78).

Equation 1.

Figure 7-2 Additional Slope Compensation

Blanking provides an interval between the FET gate drive going high and the current comparator on CS actively monitoring the input. This delay allows the normal turnon current transient (spike) to subside before the comparator is active, preventing undesired short duty cycles and premature current limiting.

The TPS23755 blanker timing is precise enough that the traditional R-C filters on CS can be eliminated. This avoids current-sense waveform distortion, which tends to get worse at light output loads. There may be some situations or designers that prefer an R-C approach, for example if the presence of R_S causes increased noise, due to adjacent noisy signals, to appear at CS pin. The TPS23755 provides a pulldown on CS (approximately 400 Ω) during the GATE OFF-time to improve sensing when an R-C filter must be used, by reducing cycle-to-cycle carry-over voltage on C_S.