SLVSH72 December   2023 TPS281C100

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SNS Timing Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Device Functional Modes
    4. 8.4 Working Mode
    5. 8.5 Feature Description
      1. 8.5.1 Accurate Current Sense
        1. 8.5.1.1 High Accuracy Sense Mode
      2. 8.5.2 Programmable Current Limit
        1. 8.5.2.1 Short-Circuit and Overload Protection
        2. 8.5.2.2 Capacitive Charging
      3. 8.5.3 Inductive-Load Switching-Off Clamp
      4. 8.5.4 Inductive Load Demagnetization
      5. 8.5.5 Full Protections and Diagnostics
        1. 8.5.5.1 Open-Load Detection
        2. 8.5.5.2 Thermal Protection Behavior
        3. 8.5.5.3 Undervoltage Lockout (UVLO) Protection
        4. 8.5.5.4 Reverse Polarity Protection
        5. 8.5.5.5 Protection for MCU I/Os
        6. 8.5.5.6 Diagnostic Enable Function
        7. 8.5.5.7 Loss of Ground
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 IEC 61000-4-4 EFT
        2. 9.2.1.2 IEC 61000-4-5 Surge
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting RILIM
        2. 9.2.2.2 Selecting RSNS
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 EMC Considerations
      2. 9.4.2 Layout Example
        1. 9.4.2.1 PWP Layout Without a GND Network
        2. 9.4.2.2 PWP Layout With a GND Network
        3. 9.4.2.3 DNT Layout Without a GND Network
      3. 9.4.3 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DNT|12
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 SNS Timing Characteristics

VS = 6 V to 60 V, TJ = –40°C to 150°C  (unless otherwise noted), parameters not tested in production
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SNS TIMING - CURRENT SENSE
tSNSION1 Settling time from rising edge of DIAG_EN
50% of VDIAG_EN to 90% of settled ISNS		 VEN= 5 V, VDIAG_EN = 0 V to 5 V, VOL_ON = 0 V , 
RSNS = 1 kΩ, IL = 1A		 15 µs
VEN = 5 V, VDIAG_EN = 0 V to 5 V,  VOL_ON = 0 V , 
RSNS = 1 kΩ, IL = 50 mA		 80 µs
tSNSION2 Settling time from rising edge of EN and DIAG_EN
50% of VDIAG_EN VEN to 90% of settled ISNS		 VEN = VDIAG_EN = 0 V to 5 V
VS = 24V RSNS = 1 kΩ, IL = 1A		 150 µs
tSNSION3 Settling time from rising edge of EN
50% of VEN to 90% of settled ISNS		 VEN = 0 V to 5 V, VDIAG_EN = 5 V
RSNS = 1 kΩ, IL = 1A		 150 µs
tSNSION4 Settling time from rising edge of OL_ON
50% of VOL_ON to 90% of settled ISNS		 VOL_ON = 0 to 5V, VEN = VDIAG_EN = 5 V
RSNS = 1 kΩ, IL = 6mA		 60 µs
tSNSION5 Settling time from falling edge of IL < IKSNS2_EN to 90% of settled ISNS VOL_ON = VEN = VDIAG_EN = 5 V
RSNS = 1 kΩ, IL = 100 mA to 10mA		 60 µs
tSNSION6 Settling time from Rising edge of IL > IKSNS2_DIS.  to  90% of settled ISNS VOL_ON = VEN = VDIAG_EN = 5 V
RSNS = 1 kΩ, IL = 10 mA to 100mA		 60 µs
tKSNS2_DIS_DGL Deglitch time for transition of IL > IKSNS2_DIS.   VOL_ON = VEN = VDIAG_EN = 5 V
RSNS = 1 kΩ, IL = 10 mA to 100mA		 30 µs
tSNSIOFF Settling time from falling edge of DIAG_EN VEN = 5 V, VDIAG_EN = 5 V to 0 V
RSNS = 1 kΩ, RL = 48 Ω		 20 µs
tSETTLEH Settling time from rising edge of load step. 
50% of VOL_ON to 90% of settled ISNS		 VEN = VDIAG_EN = 5 V
RSNS = 1 kΩ, IOUT = 0.5 A to 3 A		 20 µs
tSETTLEL Settling time from falling edge of load step. 
50% of VOL_ON to 10% of settled ISNS		 VEN = VDIAG_EN = 5 V
RSNS = 1 kΩ, IOUT = 3 A to 0.5 A		 20 µs
tTIMEOUT Time to indicate VSNSFH due to VS-VOUT>2V.

From rising edge of EN,  DIAG_EN and OL_ON
50% of VDIA_EN VEN VOL_ONto 50% of rising edge of VSNSFH		 VDIAG_EN = VEN = VOL_ON = 0 V to 5 V
RSNS = 1 kΩ, IOUT = 5 mA COUT =50µF		 245 µs
tSNSFH Assertion time for SNSFH

From 50% rising edge of VSNSFH
to 50% of falling edge of VSNSFH		 VDIAG_EN = VEN = VOL_ON = 0 V to 5 V
RSNS = 1 kΩ, IOUT = 5 mA COUT =15µF		 60 µs