The output power-protection is a line-compensated, feedback based protection to limit the output power of the system application. The FB pin voltage is compared to a ramp that is generated based on the switch on-time, the duty cycle, of each switching event. When the FB pin voltage is greater than the ramp at the negative edge of the internal PWM signal, the OPP timer increases. If the FB pin voltage is less than the OPP threshold, the timer decreases. When the timer reaches the OPP time, t_opp, of 85ms the fault is engaged and the device stops switching.

Figure 7-13 OPP Ramp

In Figure 7-14 , the output load in an application is increased which causes the control loop to increase the FB pin voltage. The increase in FB pin voltage indicates the need to deliver more power to maintain regulation. Once the FB pin is above the OPP ramp and OPP is detected, the internal OPP timer starts counting towards the t_opp limit of 85ms. Eventually the OPP timer is reached and the protection is engaged and the device stops switching.

Figure 7-14 Load Step Causing OPP

Figure 7-15 shows how the timer operation works, with a load condition that is not as long as t_opp initially, but with repetitive high load pulses the overpower protection can still engage. In an application that requires momentary power boosts, the time of the power boost pulse must be shorter than the time without a power boost to not engage OPP. Otherwise, over time, the internal timer reaches the 85ms limit to engage OPP.

Figure 7-15 OPP Timer Increasing to the OPP Timer Limit