SLUSEW0 December   2023 UCC28750

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Detailed Pin Descriptions
      1. 7.3.1 VDD - Input Bias
      2. 7.3.2 DRV - Gate Drive Out
      3. 7.3.3 CS - Current Sensing
      4. 7.3.4 FB - Feedback
      5. 7.3.5 FLT - Fault
      6. 7.3.6 GND - Ground Return
    4. 7.4 Feature Description
      1. 7.4.1 Soft Start
      2. 7.4.2 Control Law
      3. 7.4.3 Frequency Dithering
      4. 7.4.4 Fault Protections
        1. 7.4.4.1 VDD Overvoltage and Undervoltage Lockout
        2. 7.4.4.2 Internal Overtemperature Protection
        3. 7.4.4.3 Output Overpower Protection
        4. 7.4.4.4 Output Short-Circuit Protection
        5. 7.4.4.5 FLT Pin Protections
      5. 7.4.5 Slope Compensation
    5. 7.5 Device Functional Modes
      1. 7.5.1 Off
      2. 7.5.2 Startup
      3. 7.5.3 On
      4. 7.5.4 Fault
      5. 7.5.5 Disabled
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Input Bulk Capacitance with Minimum Bulk Voltage
        2. 8.2.3.2 Transformer Turns Ratio and Inductance
        3. 8.2.3.3 Current Sense and Slope Compensation Network
        4. 8.2.3.4 Output Capacitors
        5. 8.2.3.5 VDD Capacitance, CVDD
      4. 8.2.4 Application Performance Plots
        1. 8.2.4.1 Startup
        2. 8.2.4.2 Load Transients
        3. 8.2.4.3 Q1 Drain Voltage Evaluation
      5. 8.2.5 What to Do and What Not to Do
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.3.5 VDD Capacitance, CVDD

The capacitance on VDD needs to supply the device operating current until the output of the converter reaches the target minimum operating voltage. At this time the auxiliary winding can sustain the voltage to the UCC28750. The input VDD capacitance is determind by the on current of the controller and the output voltage rise time of the application. The VDD capacitor must be able to keep the VDD pin voltage above 9V, Vuvlo(off), until the output voltage reflected to the auxiliary can take over as the primary bias to the controller.

The soft start feature in UCC28750 does not ramp to full power deliver in the first steps, therefore a conservative 2ms addition is placed into Equation 27 to help size the input capacitors.

A split diode and capacitor network can be used in flyback designs to lower the initial startup time, but still have a path for a bulk capacitance on the device's input put, as shown Section 7.3.1 and reproduced here for ease of use.

GUID-20230918-SS0I-MHHV-08QN-9G3P9DKDHDQD-low.svg Figure 8-3 Split Diode Biasing Scheme for Use With Startup Resistors

The first capacitor, CVDD1, is determined by the startup resistor value and the desired turn-on time. The startup resistor values are constrained by power loss and fault requirements as mentioned in Section 7.5.4.

For a design with a typical one second start time, and a startup resistor network with an sum resistance of 1.2MΩ after adding in additional margin. The resulting CVDD1 value is approximatly 6μF. The nearest standard value is 6.8μF.

CVDD2 is largely determined by the output voltage rise time and the feedback loop estimates. Those parameters can cause an small overshoot during startup, especially at no load applications. When an overshoot occurs the device can stop switching if the feedback loop pulls down on the FB pin voltage enough to push the control law into the off state ("F" region in Figure 7-9).

The output voltage rise time is derived from the assumed power available to charge the capacitor from zero volts to the programmed output voltage. The "2ms" term added in Equation 27 is to account for the fact that the device's soft start does not output full power in the first two milliseconds which, if not added to the equation, which can understate the rise time of the output voltage.

Equation 27. t vo,rise = 1 2 C out × V out 2 P out,max + 2 ms

Typically, the crossover frequency is initially placed at one-tenth the switching frequency of the power stage. That estimate can be used to determine the initial value of CVDD2. Through experiementation and measurement, the actual crossover frequency can be determined. Using the response time estimate equation from Section 8.2.3.4, Equation 24, the overshoot of the output can be determined by modifying Equation 27 for Vout and adding the tresponse estimate into the time term. The overshoot value can then be used to determine the amount of time required for that overshoot to decay back to steady state.

Equation 28. V out,overshoot = 2 × ( t vo,rise - 2 ms + t response ) C out - V out
Equation 29. t decay = C out × V out,overshoot I load

Equation 29 is dependent on the output load. When the output load is near zero, the decay time becomes long and therefore CVDD2 must be large to survive the decay time. Experimentation and testing must be performed to determine if a "dummy load," a resistor put at the output, is required to lower the decay time if the feedback loop causes too large of an overshoot.

The time for the overshoot to reach down to steady state regulation levels uses the fundamental capacitor equation.

Equation 30. C VDD2 = I off × t decay V UVLO,on - ( V UVLO,off + 1 V )

Where

  • Ioff is the UCC28750 off-state current, typically 350μA

With the large range of tdecay from the sum of tvo,rise and tresponse to the worse case of a one second decay time, CVDD2 can range from 15μF to 70μF.