JAJSSE7 November 2023 DRV8214
PRODUCTION DATA
Table 8-31 lists the memory-mapped registers for the DRV8214_STATUS registers. All register offset addresses not listed in Table 8-31 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | FAULT | Various fault registers' status. | Section 8.6.1.1 |
1h | RC_STATUS1 | Ripple Counting Status Registers - 1. | Section 8.6.1.2 |
2h | RC_STATUS2 | Ripple Counting Status Registers - 2. | Section 8.6.1.3 |
3h | RC_STATUS3 | Ripple Counting Status Registers - 3. | Section 8.6.1.4 |
4h | REG_STATUS1 | Regulation Status Registers - (1/3). | Section 8.6.1.5 |
5h | REG_STATUS2 | Regulation Status Registers - (2/3). | Section 8.6.1.6 |
6h | REG_STATUS3 | Regulation Status Registers - (3/3). | Section 8.6.1.7 |
Complex bit access types are encoded to fit into small table cells. Table 8-32 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Reset or Default Value | ||
-n | Value after reset or the default value |
FAULT is shown in Table 8-33.
Return to the Summary Table.
Status of various fault and protection bits.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | FAULT | R | 0h | 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. |
6 | RSVD | R | 0h | Reserved. |
5 | STALL | R | 0h | When this bit is 1b, it indicates motor stall. |
4 | OCP | R | 0h | 0b during normal operation, 1b if OCP event occurs. |
3 | OVP | R | 0h | 0b during normal operation, 1b if OVP event occurs. |
2 | TSD | R | 0h | 0b during normal operation, 1b if TSD event occurs. |
1 | NPOR | R | 0h | Reset and latched low if VCC>VUVLO.
Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to Section 8.3.8.3 for further explanation. |
0 | CNT_DONE | R | 0h | Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. |
RC_STATUS1 is shown in Table 8-34.
Return to the Summary Table.
Speed estimated by the ripple counting algorithm.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | SPEED | R | 0h | Outputs the motor speed estimated by the ripple counting algorithm. |
RC_STATUS2 is shown in Table 8-35.
Return to the Summary Table.
Output corresponding to number of current ripples (1/2).
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | RC_CNT_7:0 | R | 0h | Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. |
RC_STATUS3 is shown in Table 8-36.
Return to the Summary Table.
Output corresponding to number of current ripples (2/2).
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | RC_CNT_15:8 | R | 0h | Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. |
REG_STATUS1 is shown in Table 8-37.
Return to the Summary Table.
Value corresponding to the output voltage across the motor terminals.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | VMTR | R | 0h | Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and B0h corresponds to 11 V. |
REG_STATUS2 is shown in Table 8-38.
Return to the Summary Table.
Output corresponding to current flowing through the motor.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | IMTR | R | 0h | Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. |
REG_STATUS3 is shown in Table 8-39.
Return to the Summary Table.
Internal pwm duty cycle and device id.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RSVD | R | 0h | Reserved. |
5-0 | IN_DUTY | R | 0h | Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to Section 8.3.7 for further explanation on the internal PWM generation scheme. |